Timing optimization for memory devices employing error detection coded transactions

Patent metadata

Field	Value
Publication number	US-9619316-B2
Application number	US-201213997908-A
Country	US
Kind code	B2
Filing date	Mar 26, 2012
Priority date	Mar 26, 2012
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Systems, methods, and apparatuses are directed to optimizing turnaround timing of successive transactions between a host and a memory device. The host includes framing logic that generates a write frame that includes a plurality of data bits and an error bit checksum that is appended at the end of the data bits. The host further includes a bus infrastructure configured to accommodate the transfer of the write frame to the memory device and logic that defines the turnaround time to begin at a time instant that immediately follows the transfer of the data bits of the write frame. The turnaround time measures the time delay at which a succeeding write frame is to be transferred. In this manner, the turnaround time is optimized to enable the earlier initiation of successive data operations, thereby reducing the overall latency of successive back-to-back transactions.

First claim

What is claimed is:

1. A system to reduce back-to-back data transaction latency, comprising:
a memory controller including
cyclic redundancy check (CRC) logic to generate a CRC checksum,
framing logic to form a ten unit interval (UI) data frame to have 64 bits of data in the first eight unit intervals and an 8 bit CRC checksum in the ninth unit interval, wherein a clock cycle includes two UIs,
controller transaction logic to transfer the ten UI data frame to a synchronous dynamic random access memory (SDRAM) device; and

the SDRAM device having
a DRAM core having multiple memory addresses,
DRAM transaction logic to commence a turnaround time in response to a start of a fifth clock cycle after a write latency.

2. The system of claim 1 , wherein the turnaround time is defined by a tWTR_S parameter.

3. The system of claim 1 , wherein the turnaround time is defined by a tWTR_L parameter.

4. The system of claim 1 , wherein the turnaround time is defined by a tWR parameter.

5. The system of claim 1 , wherein the SDRAM device includes a DDR4 SDRAM device.

6. The system of claim 1 , wherein the SDRAM device includes a LPDDR4 SDRAM device.

7. A synchronous dynamic random access memory (SDRAM) device, the SDRAM device comprising:
a DRAM core having multiple memory addresses;
framing logic to receive a ten unit interval (UI) data frame having 64 bits of data in the first eight unit intervals and an 8 bit CRC checksum in the ninth unit interval from a memory controller, wherein a clock cycle includes two UIs; and
transaction logic to commence a turnaround time in response to a start of a fifth clock cycle after a write latency.

8. The SDRAM device of claim 7 , wherein the turnaround time is defined by a tWTR_S parameter.

9. The SDRAM device of claim 7 , wherein the turnaround time is defined by a tWTR_L parameter.

10. The SDRAM device of claim 7 , wherein the turnaround time is defined by a tWR parameter.

11. The SDRAM device of claim 7 , wherein the SDRAM device includes a DDR4 SDRAM device.

12. The SDRAM device of claim 7 , wherein the SDRAM device includes a LPDDR4 SDRAM device.

13. A memory controller to reduce back-to-back data transaction latency, comprising:
cyclic redundancy check (CRC) logic to generate a CRC checksum,
framing logic to form a ten unit interval (UI) data frame to have 64 bits of data in the first eight unit intervals and an 8 bit CRC checksum in the ninth unit interval,
transaction logic to transfer the ten UI data frame to a synchronous dynamic random access memory (SDRAM) device, wherein a turnaround time corresponding to the ten UI data frame is initiated before the entire ten UI data frame is transferred.

14. The memory controller of claim 13 , wherein the turnaround time is defined by a tWTR_S parameter.

15. The memory controller of claim 13 , wherein the turnaround time is defined by a tWTR_L parameter.

16. The memory controller of claim 13 , wherein the turnaround time is defined by a tWR parameter.

17. The memory controller of claim 13 , wherein the SDRAM device includes a DDR4 SDRAM device.

18. The memory controller of claim 13 , wherein the SDRAM device includes a LPDDR4 SDRAM device.

Assignees

• Bains Kuljit Singh
• Intel Corp

Inventors

• Bains Kuljit Singh

Classifications

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title