Hardware apparatuses and methods for memory corruption detection

Patent metadata

Field	Value
Publication number	US-10776190-B2
Application number	US-201816224579-A
Country	US
Kind code	B2
Filing date	Dec 18, 2018
Priority date	Dec 21, 2015
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

First claim

What is claimed is:

1. A hardware processor comprising:
an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory; and
a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is in a location that does not include a most significant bit of the pointer.

2. The hardware processor of claim 1 , further comprising a control register to set the position to the location.

3. The hardware processor of claim 1 , further comprising a control register to set a memory corruption detection protected space for a subset of the memory.

4. The hardware processor of claim 3 , wherein the pointer further comprises a memory corruption detection protected space value, and the memory management unit is to allow access to the block of the memory without a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is not within the memory corruption detection protected space for the subset of the memory.

5. The hardware processor of claim 3 , wherein the pointer further comprises a memory corruption detection protected space value, and the memory management unit is to perform a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is within the memory corruption detection protected space for the subset of the memory.

6. The hardware processor of claim 1 , further comprising a register to store a base address of a memory corruption detection table in the memory comprising the memory corruption detection value for the block.

7. The hardware processor of claim 1 , wherein the position of the memory corruption detection value in the pointer in the location does not include a least significant bit of the pointer.

8. The hardware processor of claim 1 , wherein the pointer comprises a linear address of the block of the memory.

9. A method comprising:
receiving a request to access a block of a memory through a pointer to the block of the memory; and
allowing access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is in a location that does not include a most significant bit of the pointer.

10. The method of claim 9 , further comprising writing to a register to set the position to the location.

11. The method of claim 9 , further comprising setting a memory corruption detection protected space for a subset of the memory.

12. The method of claim 11 , wherein the pointer further comprises a memory corruption detection protected space value, and further comprising allowing access to the block of the memory without a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is not within the memory corruption detection protected space for the subset of the memory.

13. The method of claim 11 , wherein the pointer further comprises a memory corruption detection protected space value, and further comprising perform a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is within the memory corruption detection protected space for the subset of the memory.

14. The method of claim 9 , further comprising storing a base address of a memory corruption detection table in the memory comprising the memory corruption detection value for the block.

15. The method of claim 9 , wherein the position of the memory corruption detection value in the pointer in the location does not include a least significant bit of the pointer.

16. The method of claim 9 , wherein the pointer comprises a linear address of the block of the memory.

17. A system comprising:
a memory;
a hardware processor comprising an execution unit to execute an instruction to request access to a block of the memory through a pointer to the block of the memory; and
a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is a location that does not include a most significant bit of the pointer.

18. The system of claim 17 , further comprising a control register to set the position to the location.

19. The system of claim 17 , further comprising a control register to set a memory corruption detection protected space for a subset of the memory.

20. The system of claim 19 , wherein the pointer further comprises a memory corruption detection protected space value, and the memory management unit is to allow access to the block of the memory without a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is not within the memory corruption detection protected space for the subset of the memory.

21. The system of claim 19 , wherein the pointer further comprises a memory corruption detection protected space value, and the memory management unit is to perform a validation check of the memory corruption detection value in the pointer with the memory corruption detection value in the memory for the block when the memory corruption detection protected space value is within the memory corruption detection protected space for the subset of the memory.

22. The system of claim 17 , further comprising a register to store a base address of a memory corruption detection table in the memory comprising the memory corruption detection value for the block.

23. The system of claim 17 , wherein the position of the memory corruption detection value in the pointer in the location does not include a least significant bit of the pointer.

24. The system of claim 17 , wherein the pointer comprises a linear address of the block of the memory.

Assignees

• Intel Corp

Inventors

• Stark Tomer
• Gabor Ron
• Nuzman Joseph
• Sade Raanan
• Bigbee Bryant E

Classifications

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F2212/656

  Address space sharing · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F21/78

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title