Solar array system and method of manufacturing

Patent metadata

Field	Value
Publication number	US-10770606-B2
Application number	US-201715819196-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	Jul 27, 2015
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A space-grade solar array includes relatively small cells with integrated wiring embedded into or incorporated directly onto a printed circuit board. The integrated wiring provides an interface for solar cells having back side electrical contacts. The single side contacts enable the use of pick and place (PnP) technology in manufacturing the space-grade solar array. The solar cell is easily and efficiently packaged and electrically interconnected with other solar cells on a solar panel such as by using PnP process. The back side contacts are matched from a size and positioning standpoint to corresponding contacts on the printed circuit board.

First claim

The invention claimed is:

1. A method of manufacturing a space-grade solar array, comprising:
dicing a multi-junction solar wafer having a plurality of solar cells to form a plurality of diced multi-junction solar cells, wherein each solar cell already has a positive electrical contact and a negative electrical contact both located on a common, back side of the solar cell;
using a pick and place robot to position the diced solar cells onto a printed circuit board with the back side of each diced solar cell in contact with a front side of the printed circuit board such that the positive electrical contact and the negative electrical contact of each diced solar cell electrically couples to a corresponding electrical contact of the printed circuit board, and wherein the printed circuit board has electrical traces that include solar cell-to-solar cell interconnect wiring and bypass and blocking diodes, and wherein the positive electrical contact and the negative electrical contact of each diced solar cell has a coefficient of thermal expansion that matches a coefficient of thermal expansion of the electrical contact of the printed circuit board; and
after the plurality of diced solar cells are positioned on the printed circuit board, covering the plurality of diced solar cells with a coverglass material while the diced solar cells are positioned on the printed circuit board and bonding the coverglass material to the plurality of diced solar cells.

2. The method of claim 1 , wherein the printed circuit board is rigid.

3. The method of claim 1 , wherein the printed circuit board is flexible.

4. The method of claim 1 , wherein the printed circuit board serves as a solar array panel.

5. The method of claim 1 , further comprising positioning the printed circuit board with the solar cells onto a solar array panel.

6. The method of claim 1 , wherein the solar cell wafer is cut into solar cells that are no larger than 20 cm 2 .

7. The method of claim 1 , further comprising locating the bypass and blocking diodes onto a back side of the printed circuit board.

8. The method of claim 1 , further comprising using a pick and place robot to position the solar cells onto the printed circuit board.

9. The method of claim 1 , wherein a pick and place robot is used automatically to position the solar cells onto the printed circuit board without human intervention.

10. The method of claim 1 , wherein both the positive electrical contact and the negative electrical contact are exposed contacts.

11. The method of claim 1 , wherein the positive electrical contact and the negative electrical contact of each diced solar cell has a size that matches a size of respective electrical contact of the printed circuit board.

12. The method of claim 1 , wherein only the diced solar cells are positioned on the printed circuit board.

13. The method of claim 12 , further comprising removing and replacing a single solar cell from the printed circuit board.

14. The method of claim 12 , further comprising removing and replacing a single solar cell from the printed circuit board without affecting a power capability of the entire solar array.

15. The method of claim 12 , further comprising placing only bypass and blocking diodes on a back side of the printed circuit board.

16. The method of claim 1 , further comprising removing and replacing a single solar cell from the printed circuit board.

17. A method of manufacturing a space-grade solar array, comprising:
dicing a multi junction solar wafer having a plurality of solar cells to form a diced multi-junction solar cell, wherein the diced solar cell already has a positive electrical contact and a negative electrical contact both located on a common, back side of the diced solar cell;
covering the diced solar cell with a protective coverglass, wherein the coverglass is a space-grade, radiation protective coverglass;
using a pick and place robot to position the diced solar cells onto a printed circuit board with the back side of the diced solar cell in contact with a front side of the printed circuit board such that the positive electrical contact and the negative electrical contact of the diced solar cell electrically couples to a corresponding electrical contact of the printed circuit board, and wherein the printed circuit board has electrical traces that include solar cell-to-solar cell interconnect wiring and bypass and blocking diodes, and wherein the positive electrical contact and the negative electrical contact of the diced solar cell has a coefficient of thermal expansion that matches a coefficient of thermal expansion of the electrical contact of the printed circuit board, wherein only the diced solar cells are positioned on the printed circuit board.

18. The method of claim 17 , wherein the printed circuit board is rigid.

19. The method of claim 17 , wherein the printed circuit board is flexible.

20. The method of claim 17 , wherein the printed circuit board serves as a solar array panel.

21. The method of claim 17 , further comprising positioning the printed circuit board with the solar cells onto a solar array panel.

22. The method of claim 17 , wherein the solar cell wafer is cut into solar cells that are no larger than 20 cm 2 .

23. The method of claim 17 , further comprising locating the bypass and blocking diodes onto a back side of the printed circuit board.

24. The method of claim 17 , further comprising using a pick and place robot to position the solar cells onto the printed circuit board.

25. The method of claim 17 , wherein a pick and place robot is used automatically to position the solar cells onto the printed circuit board without human intervention.

26. The method of claim 17 , wherein both the positive electrical contact and the negative electrical contact are exposed contacts.

Assignees

• Sierra Nevada Corp

Inventors

• Anthony Brian
• Dobson Rodney
• Johnson Matthew
• Christiansen Scott
• Ruhl L Eric

Classifications

• H10P72/0438

  Apparatus for making assemblies not otherwise provided for, e.g. package constructions · CPC title

• H10P72/0428

  Apparatus for mechanical treatment or grinding or cutting · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10F77/219

  Arrangements for electrodes of back-contact photovoltaic cells · CPC title