Pin access hybrid cell height design

Patent metadata

Field	Value
Publication number	US-10769342-B2
Application number	US-201916556928-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Oct 31, 2018
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A method of generating an integrated circuit layout diagram includes arranging first cells having a first cell height in a first row and arranging second cells having a second cell height less than the first cell height in a second row abutting the first row. The first row and the second row extend along a first direction and are laid out relative to a routing grid including first routing tracks along the first direction and second routing tracks along a second direction perpendicular to the first direction. First cell pins are placed within each first cell extending along second routing tracks. Second cell pins are placed over selected via placement points in each second cell. At least one second cell pin extends along a corresponding second routing track across a boundary of a corresponding second cell and into a corresponding first cell abutting the corresponding second cell.

First claim

What is claimed is:

1. A method of generating a layout diagram for an integrated circuit, the method comprising:
arranging a plurality of first cells having a first cell height in a first row;
arranging a plurality of second cells having a second cell height in a second row abutting the first row, wherein the second cell height is less than the first cell height, and the first row and the second row extend along a first direction and are laid out relative to a routing grid comprising a plurality of first routing tracks extending along the first direction and a plurality of second routing tracks extending along a second direction perpendicular to the first direction;
placing a plurality of first cell pins within each first cell of the plurality of first cells, wherein each of the plurality of first cell pins extends along a corresponding second routing track of the plurality of second routing tracks; and
placing a plurality of second cell pins over a plurality of selected via placement points in each second cell of the plurality of second cells, wherein at least one second cell pin of the plurality of second cell pins extends along a corresponding second routing track of the plurality of second routing tracks across a boundary of a corresponding second cell of the plurality of second cells and into a corresponding first cell of the plurality of first cells abutting the corresponding second cell.

2. The method of claim 1 , further comprising identifying a plurality of via placement points in each second cell of the plurality of second cells at corresponding intersections between the plurality of first routing tracks and the plurality of second routing tracks, wherein the plurality of via placement points are possible locations for placing the plurality of second cell pins.

3. The method of claim 2 , further comprising identifying the plurality of selected via placement points from the plurality of via placement points for each second cell of the plurality of second cells such that after placing the plurality of second cell pins over the plurality of selected via placement points, facing ends of adjacent first cell pin and second cell pin on a same routing track are separated by a distance equal to or greater than a minimum end-to-end spacing according to a set of design rules.

4. The method of claim 1 , wherein each of the plurality of first cell pins is placed such that opposite ends of each of the plurality of first cell pins are terminated within top and bottom boundaries of a corresponding first cell of the plurality of first cells.

5. The method of claim 1 , wherein the at least one second cell pin of the plurality of second cell pins is placed such that an end of the at least one second cell pin of the plurality of second cell pins is terminated within top and bottom boundaries of the corresponding second cell of the plurality of second cells, and an opposite end of the at least one second cell pin of the plurality of second cell pins is terminated within the corresponding first cell of the plurality of first cells abutting the corresponding second cell of the plurality of second cells.

6. The method of claim 1 , wherein at least another second cell pin of the plurality of second cell pins is placed such that opposite ends of the at least another second cell pin of the plurality of second cell pins are terminated at top and bottom boundaries of the corresponding second cell of the plurality of second cells.

7. The method of claim 1 , further comprising elongating at least one first cell pin of the plurality of first cell pins along a corresponding second routing track of the plurality of second routing tracks to across a boundary of a corresponding first cell where the at least one first cell pin is located.

8. The method of claim 1 , further comprising elongating at least one second cell pin of the plurality of second cell pins along a corresponding second routing track of the plurality of second routing tracks, wherein a distance between facing ends of the at least one elongated second cell pin of the plurality of second cell pins and an adjacent first cell pin on a same second routing track with the at least one elongated second cell pin is equal to or greater than a minimum end-to-end spacing according to a set of design rules.

9. The method of claim 1 , further comprising placing a plurality of first conductive lines along a first set of first routing tracks of the plurality of first routing tracks for the plurality of first cells, and a plurality of second conductive lines along a second set of first routing tracks of the plurality of first routing tracks for the plurality of second cells.

10. The method of claim 9 , further comprising placing a plurality of first vias to couple the plurality of first conductive lines with the plurality of first cell pins.

11. The method of claim 9 , further comprising placing a plurality of second vias to couple the plurality of second conductive lines with the plurality of second cell pins.

12. A method of generating a layout diagram for an integrated circuit, the method comprising:
arranging a plurality of first cells having a first cell height in a plurality of first rows;
arranging a plurality of second cells having a second cell height less than the first cell height in a plurality of second rows, wherein the plurality of first rows and the plurality of second rows are laid out according to a routing grid comprising a plurality of first routing tracks extending in a first direction and a plurality of second routing tracks extending in a second direction perpendicular to the first direction;
placing a plurality of first cell pins over a plurality of selected first via placement points in each first cell of the plurality of first cells, wherein each first cell pin of the plurality of first cell pins extends along a corresponding second routing track of the plurality of second routing track and has both ends terminated within top and bottom boundaries of a corresponding first cell of the plurality of first cells; and
placing a plurality of second cell pins over a plurality of selected via placement points in each second cell of the plurality of second cells, wherein at least one second cell pin of the plurality of second cell pins extends along a corresponding second routing track of the plurality of second routing tracks across a boundary of a corresponding second cell of the plurality of second cells and into a corresponding first cell of the plurality of first cells abutting the corresponding second cell.

13. The method of claim 12 , further comprising identifying a plurality of first via placement points within each first cell of the plurality of first cells and a plurality of second via placement points within each second cell of the plurality of second cells, wherein each of the plurality of first via placement points and the plurality of second via placement points is at an intersection of a corresponding first routing track of the plurality of first routing tracks and a corresponding second routing track of the plurality of second routing tracks.

14. The method of claim 12 , further comprising identifying the plurality of selected first via placement points from the plurality of first via placement points and identifying the plurality of selected second via placement points from the plurality of second via placement points such that after placing the plurality of first cell pins on the plurality of selected first via placement points and placing the plurality of second cell pins on the plurality of selected second via placement points, facing ends of adjacent first cell pin and second cell pin on

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Sio Kam-Tou
• Tzeng Jiann-Tyng

Classifications

• H10W72/50

  Bond wires · CPC title

• G06F30/3953

  detailed · CPC title

• G06F30/3947

  global · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title