Partial response receiver

Patent metadata

Field	Value
Publication number	US-10764094-B2
Application number	US-201916287941-A
Country	US
Kind code	B2
Filing date	Feb 27, 2019
Priority date	Apr 9, 2003
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

First claim

What is claimed is:

1. A receiver integrated circuit comprising:
sampling circuitry to sample a multi-PAM input symbol, the sampling circuitry to sample the symbol and generate multi-bit sample values that indicate whether the symbol exceeds respective threshold levels, each of the threshold levels used to resolve a given multi-PAM input symbol into a corresponding multi-bit sample value; and
an adaptive module coupled to the sampling circuitry, the adaptive module to adjust the threshold levels based on signal levels produced by selected data patterns.

2. The receiver integrated circuit according to claim 1 , wherein:
the multi-PAM input symbol comprises a 4-PAM input symbol.

3. The receiver integrated circuit according to claim 2 , wherein:
the sampling circuitry comprises a receive circuit operable to resolve a signal level of the 4-PAM input symbol into one of four possible multi-bit combinations.

4. The receiver integrated circuit according to claim 3 , wherein:
the threshold levels define four voltage ranges, each voltage range representing a multi-bit value for a given received input symbol having a voltage level corresponding to one of the four voltage ranges.

5. The receiver integrated circuit according to claim 1 , further comprising:
a select circuit to receive the multi-bit sample values from the sampling circuitry and to select, based at least in part upon at least one previously sampled value, at least one of the multi-bit sample values.

6. The receiver integrated circuit according to claim 1 , wherein the sampling circuitry includes comparison circuitry to compare the received input symbol to a respective threshold level that is offset from a corresponding one of the four data levels according to one of four partial response levels.

7. The receiver integrated circuit according to claim 6 , wherein:
the sampling circuitry is operable to resolve the input symbol into at least four two-bit sample values according to each of the four possible partial responses to the preceding symbol.

8. The receiver integrated circuit according to claim 1 , further comprising:
clock recovery circuitry coupled to the sampling circuitry, the clock recovery circuitry to extract timing information from the received multi-PAM input symbol.

9. An integrated circuit (IC) chip, comprising:
receiver circuitry, wherein the receiver circuitry includes
sampling circuitry to sample a multi-PAM input symbol, the sampling circuitry to sample the symbol and generate multi-bit sample values that indicate whether the symbol exceeds respective threshold levels, each of the threshold levels used to resolve a given multi-PAM input symbol into a corresponding multi-bit sample value; and

an adaptive module coupled to the sampling circuitry, the adaptive module to adjust the threshold levels based on signal levels produced by selected data patterns.

10. The receiver integrated circuit according to claim 9 , wherein:
the multi-PAM input symbol comprises a 4-PAM input symbol.

11. The receiver integrated circuit according to claim 10 , wherein:
the sampling circuitry comprises a receive circuit operable to resolve a signal level of the 4-PAM input symbol into one of four possible multi-bit combinations.

12. The receiver integrated circuit according to claim 11 , wherein:
the threshold levels define four voltage ranges, each voltage range representing a multi-bit value for a given received input symbol having a voltage level corresponding to one of the four voltage ranges.

13. The receiver integrated circuit according to claim 9 , further comprising:
a select circuit to receive the multi-bit sample values from the sampling circuitry and to select, based at least in part upon at least one previously sampled value, at least one of the multi-bit sample values.

14. The receiver integrated circuit according to claim 9 , wherein the sampling circuitry includes comparison circuitry to compare the received input symbol to a respective threshold level that is offset from a corresponding one of the four data levels according to one of four partial response levels.

15. The receiver integrated circuit according to claim 14 , wherein:
the sampling circuitry is operable to resolve the input symbol into at least four two-bit sample values according to each of the four possible partial responses to the preceding symbol.

16. The receiver integrated circuit according to claim 9 , further comprising:
clock recovery circuitry coupled to the sampling circuitry, the clock recovery circuitry to extract timing information from the received multi-PAM input symbol.

17. A method of operation for a receiver integrated circuit, comprising:
sampling a multi-PAM input symbol with sampling circuitry, the sampling to generate multi-bit sample values that indicate whether the symbol exceeds respective threshold levels, each of the threshold levels used to resolve a given multi-PAM input symbol into a corresponding multi-bit sample value; and
adjusting the threshold levels with an adaptive module, the adjusting based on signal levels produced by selected data patterns.

18. The method according to claim 17 , wherein the sampling comprises:
sampling a 4-PAM input symbol with the sampling circuitry.

19. The method according to claim 18 , wherein the sampling comprises:
resolving a signal level of the 4-PAM input symbol into one of four possible multi-bit combinations.

20. The method according to claim 17 , further comprising:
receiving the multi-bit sample values from the sampling circuitry; and
selecting, based at least in part upon at least one previously sampled value, at least one of the multi-bit sample values.

Assignees

• Rambus Inc

Inventors

• Stojanovic Vladimir M
• Ho Andrew C
• Bessios Anthony
• Garlepp Bruno W
• Tsang Grace
• Horowitz Mark A
• Zerbe Jared L
• Wei Jason C

Classifications

• H04L25/497 Primary

  by correlative coding, e.g. partial response coding or echo modulation coding {transmitters and receivers for partial response systems (transversal equalizers at the transmitter end H04L25/03343)} · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/063

  Setting decision thresholds using feedback techniques only · CPC title

• H04L7/0276

  Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate · CPC title

• H04L2025/03369

  Partial response · CPC title