Partial response receiver

Patent metadata

Field	Value
Publication number	US-9917708-B2
Application number	US-201615092435-A
Country	US
Kind code	B2
Filing date	Apr 6, 2016
Priority date	Apr 9, 2003
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

First claim

What is claimed is:

1. A method of operation in a receiver integrated circuit comprising:
sampling an input symbol with a plurality of sampling circuits, the input symbol representing at least two bits of information and having one of at least four data levels, the sampling for each of the plurality of sampling circuits including sampling the signal and generating a sample value that indicates whether the signal exceeds a respective threshold level;
receiving the sample values from the plurality of sampling circuits with a select circuit, and selecting, based at least in part upon at least one previously sampled value, at least one of the sample values; and
storing the at least one previously sampled value in storage, and providing the at least one previously sampled value to the select circuit.

2. The method according to claim 1 , wherein the sampling of the input symbol comprises sampling the input symbol with at least four receive circuits, each receive circuit resolving a signal level of the input symbol into one of four possible two-bit combinations.

3. The method according to claim 2 , further comprising:
adaptively determining values for the threshold levels with an adaptive module included in each of the at least four receiver circuits.

4. The method according to claim 2 , further comprising:
adaptively determining values for the threshold levels with an adaptive module shared by the at least four receive circuits.

5. The method according to claim 1 , wherein the sampling includes comparing, with comparison circuitry, the received input symbol to a respective threshold level that is offset from a corresponding one of the four data levels according to one of four partial response levels.

6. The method according to claim 2 , wherein:
the resolving includes resolving the input symbol into at least four two-bit sample values according to each of the four possible partial responses to the preceding symbol.

7. The method according to claim 1 , wherein:
the input symbol comprises a 4-PAM signal.

8. The method according to claim 1 , further comprising:
receiving the at least one selected sampled value with a clock data recovery circuit, and generating in dependence thereon a sampling clock signal, and sampling the respective data level in dependence on the sampling clock signal with each of the plurality of sampling circuits.

9. A method of operation in a receiver integrated circuit that includes plural receive circuits and a mode select circuit, the method comprising:
configuring, with the mode select circuit, in response to a mode select signal, the plural receive circuits into one of a multi-level receiver to receive an input data symbol representing at least two bits of information and having one of at least four levels or a 2-PAM partial response receiver to receive an input data symbol having one of two levels;
comparing, with comparison circuitry in the multi-level receiver, the input symbol to at least four respective threshold level control values; and
using at least a portion of the comparison circuitry, with the 2-PAM partial response receiver, to compare the input data symbol to respective partial response threshold levels.

10. The method according to claim 9 , further comprising:
adaptively generating the threshold level control values and the partial response threshold levels with an adaptive module.

11. The method according to claim 9 wherein the plural receive circuits comprise four receive circuits, and wherein the method further comprises:
using first and second receive circuits from the plural receive circuits in the 2-PAM partial response receiver to compare the input data symbol to respective partial response threshold levels.

12. The method according to claim 9 , further comprising:
using a third receive circuit from the plural receive circuits in the 2-PAM partial response receiver to generate the partial response levels.

13. The method according to claim 9 , further comprising:
providing the mode select signal from an external source.

14. The method according to claim 9 , further comprising:
providing the mode select signal to the mode select circuit via a configuration control circuit.

15. The method according to claim 14 , wherein the configuration control circuit includes a configuration register, and wherein the providing comprises storing the mode select signal in the configuration register.

16. The method according to claim 14 , wherein the providing of the mode select signal further comprises dynamically changing the state of the mode select signal in response to system conditions detected by the configuration control circuit.

17. The method according to claim 9 , further comprising:
receiving selected sampled values with a clock data recovery circuit, and generating in dependence thereon a sampling clock signal, and sampling, with each of the plural receive circuits, the respective data signal in dependence on the sampling clock signal.

18. A method of operation in a receiver integrated circuit comprising:
generating data samples with a level sampler circuit responsive to a sampling clock signal, the level sampler circuit including plural receive circuits;
configuring the plural receive circuits into one of a 4-PAM receiver to receive an input data symbol representing at least two bits of information and having one of at least four data levels or a 2-PAM partial response receiver to receive an input data symbol having one of two levels;
capturing transition samples with an edge sampler circuit in response to transitions of an edge clock signal; and
selectively adjusting a phase of the edge clock signal and a phase of the sampling clock signal with a clock data recovery circuit based on the transition samples and data samples.

19. The method according to claim 18 , further comprising:
configuring the plural receive circuits with a mode select circuit responsive to a mode select signal into one of the multi-level receiver or the 2-PAM partial response receiver.

20. The method according to claim 19 , further comprising:
adaptively generating threshold level control values for the multi-level receiver and partial response threshold levels for the 2-PAM partial response receiver.

21. A receiver integrated circuit comprising:
a plurality of sampling circuits to sample an input symbol representing at least two bits of information and having one of at least four data levels, each of the sampling circuits to sample the signal and generate a sample value that indicates whether the signal exceeds a respective threshold level;
a select circuit to receive the sample values from the plurality of sampling circuits and to select, based at least in part upon at least one previously sampled value, at least one of the sample values; and
storage to store the at least one previously sampled value, and to provide the at least one previously sampled value to the select circuit.

Assignees

• Rambus Inc

Inventors

• Stojanovic Vladimir M
• Ho Andrew C
• Bessios Anthony
• Garlepp Bruno W
• Tsang Grace
• Horowitz Mark A
• Zerbe Jared L
• Wei Jason C

Classifications

• H04L7/0276

  Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate · CPC title

• H04L25/063

  Setting decision thresholds using feedback techniques only · CPC title

• H04L25/497 Primary

  by correlative coding, e.g. partial response coding or echo modulation coding {transmitters and receivers for partial response systems (transversal equalizers at the transmitter end H04L25/03343)} · CPC title

• H04L2025/03503

  as a combination of feedback and prediction filters · CPC title

• H04L2025/03369

  Partial response · CPC title