Partial response receiver

Patent metadata

Field	Value
Publication number	US-9407473-B2
Application number	US-201514683081-A
Country	US
Kind code	B2
Filing date	Apr 9, 2015
Priority date	Apr 9, 2003
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

First claim

What is claimed is:

1. A receiver integrated circuit comprising:
a plurality of sampling circuits to sample an input symbol having one of at least four data levels, each of the sampling circuits to sample the signal and generate a sample value that indicates whether the signal exceeds a respective threshold level;
a select circuit to receive the sample values from the plurality of sampling circuits and to select, based at least in part upon at least one previously sampled value, at least one of the sample values; and
storage to store the at least one previously sampled value, and to provide the at least one previously sampled value to the select circuit.

2. The receiver integrated circuit according to claim 1 , wherein the plurality of sampling circuits comprises at least four receive circuits, each receive circuit operable to resolve a signal level of the input symbol into one of four possible two-bit combinations.

3. The receiver integrated circuit according to claim 2 , wherein each receiver circuit further comprises:
a level sampler; and
an adaptive module to adaptively determine values for the threshold levels.

4. The receiver integrated circuit according to claim 2 , wherein:
the receiver circuits share a common level sampler and a common adaptive module to adaptively determine values for the threshold levels.

5. The receiver integrated circuit according to claim 1 , wherein each of the plurality of sampling circuits includes comparison circuitry to compare the received input symbol to a respective threshold level that is offset from a corresponding one of the four data levels according to one of four partial response levels.

6. The receiver integrated circuit according to claim 3 , wherein:
the plurality of sampling circuits is operable to resolve the input symbol into at least four two-bit sample values according to each of the four possible partial responses to the preceding symbol.

7. The receiver integrated circuit according to claim 1 , wherein:
the input symbol comprises a 4-PAM signal.

8. The receiver circuit according to claim 1 , further comprising:
a clock data recovery circuit coupled to receive the at least one selected sampled value, and operable to generate in dependence thereon a sampling clock signal, and wherein each of the plurality of sampling circuits is operable to sample the respective data signal in dependence on the sampling clock signal.

9. A multi-mode receiver integrated circuit comprising:
plural receive circuits;
a mode select circuit responsive to a mode select signal to configure the plural receive circuits into one of a multi-level receiver to receive an input data symbol having one of at least four levels or a 2-PAM partial response receiver to receive an input data symbol having one of two levels;
wherein the multi-level receiver includes comparison circuitry to compare the input symbol to at least four respective threshold level control values; and
wherein the 2-PAM partial response receiver uses at least a portion of the comparison circuitry to compare the input data symbol to respective partial response threshold levels.

10. The multi-mode receiver circuit according to claim 9 , further comprising:
an adaptive module to adaptively generate the threshold level control values and the partial response threshold levels.

11. The multi-mode receiver circuit according to claim 9 wherein:
the plural receive circuits comprise four receive circuits; and
wherein the 2-PAM partial response receiver uses first and second receive circuits from the plural receive circuits to compare the input data symbol to respective partial response threshold levels.

12. The multi-mode receiver circuit according to claim 9 , wherein:
the 2-PAM partial response receiver uses a third receive circuit from the plural receive circuits to generate the partial response levels.

13. The multi-mode receiver circuit according to claim 9 , wherein:
the mode select signal is provided from an external source.

14. The multi-mode receiver circuit according to claim 9 , further comprising:
a configuration control circuit to provide the mode select signal to the mode select circuit.

15. The multi-mode receiver circuit according to claim 14 , wherein:
the configuration control circuit includes a configuration register; and
the mode select signal is stored in the configuration register.

16. The multi-mode receiver circuit according to claim 14 , wherein:
the configuration control circuit is operable to dynamically change the state of the mode select signal in response to detected system conditions.

17. The multi-mode receiver circuit according to claim 9 , further comprising:
a clock data recovery circuit coupled to receive selected sampled values, and operable to generate in dependence thereon a sampling clock signal, and wherein each of the plural receive circuits is operable to sample the respective data signal in dependence on the sampling clock signal.

18. The multi-mode receiver circuit according to claim 9 , further comprising:
an adaptive module to adaptively generate threshold level control values for the multi-level receiver and partial response threshold levels for the 2-PAM partial response receiver.

19. A multi-mode receiver integrated circuit comprising:
a level sampler circuit responsive to a sampling clock signal to generate data samples, the level sampler circuit including plural receive circuits operable to be configured into one of a 4-PAM receiver to receive an input data symbol having one of at least four data levels or a 2-PAM partial response receiver to receive an input data symbol having one of two levels;
an edge sampler circuit to capture transition samples in response to transitions of an edge clock signal; and
a clock data recovery circuit operable to selectively adjust a phase of the edge clock signal and a phase of the sampling clock signal based on the transition samples and data samples.

20. The multi-mode receiver integrated circuit according to claim 19 , further comprising:
a mode select circuit responsive to a mode select signal to configure the plural receive circuits into one of the multi-level receiver or the 2-PAM partial response receiver.

Assignees

• Rambus Inc

Inventors

• Stojanovic Vladimir M
• Ho Andrew C
• Bessios Anthony
• Garlepp Bruno W
• Tsang Grace
• Horowitz Mark A
• Zerbe Jared L
• Wei Jason C

Classifications

• H04L25/063

  Setting decision thresholds using feedback techniques only · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L2025/03369

  Partial response · CPC title

• H04L2025/03503

  as a combination of feedback and prediction filters · CPC title

• H04L7/0276

  Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate · CPC title