Cascade tunneling field effect transistors

Patent metadata

Field	Value
Publication number	US-10763367-B2
Application number	US-201916407771-A
Country	US
Kind code	B2
Filing date	May 9, 2019
Priority date	May 9, 2018
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A tunnel field-effect transistor (TFET) includes a fin, an insulator layer, and at least one gate. The fin has a doped first region, a doped second region, and an interior region between the first region and the second region. The interior region is undoped or is more lightly doped than the first region and the second region. At least the interior region of the fin formed as a type II superlattice, wherein materials of the superlattice alternate vertically. The insulator layer is formed around the interior region. The gate is formed on at least a portion of the insulator region. The insulator layer and the at least one gate are configured to generate an inhomogeneous electrostatic potential within the interior region.

First claim

The invention claimed is:

1. A tunnel field-effect transistor (TFET) comprising:
a fin have a doped first region, a doped second region, and an interior region between the first region and the second region, the interior region being undoped or more lightly doped than the first region and the second region, at least the interior region of the fin formed as a type II superlattice, wherein materials of the superlattice alternate vertically;
an insulator layer formed around the interior region;
at least one gate formed on at least a portion of the insulator region;
wherein the insulator layer and the at least one gate are configured to generate an inhomogeneous electrostatic potential within the interior region.

2. The TFET of claim 1 , wherein the interior region is undoped.

3. The TFET of claim 1 , wherein the superlattice comprises alternating layers of any of the following material pairs: InAs/GaSb, InAs/AlSb, InAs/GalnSb, InAsSb/InSb, InAlN/GaN, AlGaAs/AlAs, AlGaAs/GaAs, ZnSe/ZnTe.

4. The TFET of claim 1 , wherein the superlattice includes any of the following materials: metal dichalcogenides, phosphorene, graphene, silicone, germanene, stanine, MoS2/MoTe2, SiGe/Si, metal oxide, type IV semiconductor material, type III/V semiconductor material, or type II/VI semiconductor material.

5. The TFET of claim 1 , wherein the first gate and the second gate comprises a metal or a heavily doped semiconductor.

6. The TFET of claim 1 , wherein the at least one gate comprises a first gate and a separate second gate, a top portion of the first gate extending over a top of the interior region, and a bottom portion of the second gate extending under the bottom of the interior region, wherein the top portion and the second portion have different thickenesses.

7. The TFET of claim 6 , wherein an electrostatic potential gradient within the first gate and the second gate are configured to be substantially equal to zero.

8. The TFET of claim 1 , wherein at least one of the first region and the second region are also formed from the type II superlattice.

9. The TFET of claim 8 , wherein the first region is p-doped, and the second region is n-doped.

10. The TFET of claim 1 , wherein the first region is p-doped, and the second region is n-doped.

11. The TFET of claim 1 , wherein a top portion of the at least one gate has a greater thickness than a bottom portion of the at least one gate.

12. The TFET of claim 1 , wherein the insulator layer has a substantially uniform thickness.

13. The TFET of claim 1 , wherein the insulator layer has a varying thickness.

14. The TFET of claim 1 , wherein all layers of the superlattice have the substantially the same width.

15. The TFET of claim 1 , wherein layers of the superlattice portion have different widths to form a taper.

16. A tunnel field-effect transistor (TFET) comprising:
a fin have a doped first region, a doped second region, and an interior region between the first region and the second region, the interior region being undoped or more lightly doped than the first region and the second region, at least the interior region of the fin formed as a type II superlattice, wherein materials of the superlattice alternate vertically;
an insulator layer formed around the interior region;
at least one gate formed on at least a portion of the insulator region;
wherein the fin extends in a current direction from the first region to the second region and through the interior region, wherein the insulator layer and the at least one gate are configured to apply an electric field perpendicular to the current direction when voltage is applied to the at least one gate.

17. The TFET of claim 16 , wherein the at least one gate comprises a first gate and a separate second gate, a top portion of the first gate extending over a top of the interior region, and a bottom portion of the second gate extending under the bottom of the interior region, wherein the top portion and the second portion have different thickenesses.

18. The TFET of claim 16 , wherein at least one of the first region and the second region are also formed from the type II superlattice.

19. The TFET of claim 16 , wherein the first region is p-doped, and the second region is n-doped.

20. The TFET of claim 16 , wherein a top portion of the at least one gate has a greater thickness than a bottom portion of the at least one gate.

Assignees

• Purdue Research Foundation

Inventors

• Kubis Tillmann C
• Sarangapani Prasad

Classifications

• H10D62/8163

  comprising long-range structurally-disordered materials, e.g. one-dimensional vertical amorphous superlattices · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6215 Primary

  having multiple independently-addressable gate electrodes · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H01L29/154

  Electricity · mapped topic