Method for manufacturing a semiconductor device having a Schottky contact

Patent metadata

Field	Value
Publication number	US-10763339-B2
Application number	US-201615040353-A
Country	US
Kind code	B2
Filing date	Feb 10, 2016
Priority date	Feb 11, 2015
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A semiconductor device includes an n-doped monocrystalline semiconductor substrate having a substrate surface, an amorphous n-doped semiconductor surface layer at the substrate surface of the n-doped monocrystalline semiconductor substrate, and a Schottky-junction forming material in contact with the amorphous n-doped semiconductor surface layer. The Schottky-junction forming material forms at least one Schottky contact with the amorphous n-doped semiconductor surface layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device having at least one Schottky contact, the method comprising: providing a semiconductor substrate having a substrate surface; pre-treating the semiconductor substrate by subjecting the substrate surface to a capacitively coupled plasma, wherein power which is capacitively coupled into the plasma is in a range from 0 W to 80 W; wherein the capacitively coupled plasma is carried out for less than 120 s; and sputtering a Schottky-junction forming material directly on the pre-treated substrate surface to form a Schottky contact that forms a Schottky barrier at an interface between the Schottky-junction forming material and the semiconductor substrate.

2. The method of claim 1 , wherein the Schottky-junction forming material is selected from the group consisting of molybdenum, molybdenum nitride, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, polysilicon having a doping concentration of at least 10 17 /cm 3 , and any combination thereof.

3. The method of claim 1 , further comprising pre-cleaning the substrate surface prior to pre-treating the semiconductor substrate, wherein the pre-cleaning comprises wet-chemical pre-cleaning, sputtering pre-cleaning, reactive sputtering pre-cleaning, or any combination thereof.

4. The method of claim 3 , wherein the wet-chemical pre-cleaning comprises cleaning the substrate surface with a first cleaning solution comprising distilled water, H 2 O 2 and ammonium hydroxide and/or with a second cleaning solution comprising distilled water, H 2 O 2 and hydrochloric acid.

5. The method of claim 3 , wherein the sputtering pre-cleaning and/or the reactive sputtering pre-cleaning comprises subjecting the substrate surface to a capacitively coupled plasma at a power which is larger than the power for the pre-treating, wherein the power for the sputtering pre-cleaning and/or the reactive sputtering pre-cleaning is at least 40 W.

6. The method of claim 1 , wherein the pre-treating of the substrate surface results in formation of an amorphous n-doped semiconductor surface layer.

7. The method of claim 6 , further comprising determining a presence and a thickness of the amorphous n-doped semiconductor surface layer using a focused ion beam cut in combination with scanning electron microscope analyses.

8. The method of claim 1 , wherein the pre-treating of the substrate surface is carried out such that the Fermi level at the substrate surface is pinned to a predetermined value.

9. The method of claim 1 , wherein the processes of pre-treating the substrate surface and sputtering the Schottky-junction forming material onto the pre-treated substrate surface are carried out in the same process chamber.

10. The method of claim 9 , wherein at least one of the following processes are also carried out in the same process chamber:
pre-cleaning the substrate surface;
sputtering the Schottky-junction forming material onto the pre-treated substrate surface; and
forming a metallization on the sputtered Schottky-junction forming material.

11. The method of claim 1 , wherein the Schottky-junction forming material is sputtered onto the pre-treated substrate surface in a nitrogen-containing atmosphere.

12. The method of claim 1 , wherein the semiconductor substrate comprises an n-doped region comprising an exposed portion which is exposed at the substrate surface, wherein the exposed portion of the n-doped region is pre-treated by subjecting the substrate surface to the capacitively coupled plasma, and wherein the Schottky-junction forming material is in direct contact with the exposed portion of the n-doped region.

13. The method of claim 1 , further comprising adjusting a defect density of the semiconductor substrate by varying an ambient pressure during the pre-treating step.

14. The method of claim 1 , further comprising adjusting a geometrical depth of defects in the semiconductor substrate by adjusting the power which is capacitively coupled into the plasma.

15. The method of claim 1 , wherein the pre-treating of the semiconductor substrate partially etches the semiconductor substrate, wherein a total etching is less than 10 nm of SiO 2 equivalent removal.

16. A method for manufacturing a semiconductor device having at least one Schottky contact, the method comprising:
providing a semiconductor substrate having a substrate surface;
pre-treating the semiconductor substrate by subjecting the substrate surface to a capacitively coupled plasma for less than 120 s at a pressure of less than 0.11 Pa (0.8 mTorr); and
sputtering a Schottky-junction forming material directly onto the pre-treated substrate surface to form a Schottky contact that forms a Schottky barrier at an interface between the Schottky-junction forming material and the pre-treated substrate surface.

17. The method of claim 16 , wherein the semiconductor substrate comprises SiC, Si, SiGe, GaAs, GaN, AlGaAs, GaInP, III-V compound semiconductors such as GaAsP, (III,III)-V compound semiconductors, III-(V,V) compound semiconductors, or diamond.

18. The method of claim 16 , wherein pre-treating the semiconductor substrate comprises subjecting the substrate surface to an argon plasma discharge, wherein power which is capacitively coupled into the plasma is in a range from 0 W to 80 W.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Konrath Jens Peter
• Kern Ronny
• Krivec Stefan
• Schmid Ulrich
• Stoeber Laura

Classifications

• H10D64/0123

  to silicon carbide · CPC title

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P14/3454

  Amorphous · CPC title