Programmable receivers including a delta-sigma modulator

Patent metadata

Field	Value
Publication number	US-10756751-B2
Application number	US-201816176714-A
Country	US
Kind code	B2
Filing date	Oct 31, 2018
Priority date	May 9, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may also include a first summing node having an output coupled to an input of the first integrator, and a feedforward path from an input of the delta sigma loop filter to a first input of the first summing node. Further, each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first feedback path from an output of the quantizer to a second input of the first summing node.

First claim

We claim:

1. A programmable delta-sigma modulator, comprising:
a first channel configured to receive an in-phase signal and including a first delta-sigma loop filter; and
a second channel configured to receive a quadrature signal and including a second delta-sigma loop filter;
each of the first delta-sigma loop filter and the second delta-sigma loop filter comprising:
a first integrator;
a quantizer having an input coupled to an output of the first integrator;
a first summing node having an output coupled to an input of the first integrator;
a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node; and
a first feedback path from an output of the quantizer to a second input of the first summing node; and

a selection unit for:
selecting one of the first channel and the second channel responsive to a low-pass mode of operation; and
selecting the other one of the first channel and the second channel responsive to a quadrature mode of operation.

2. The programmable delta-sigma modulator of claim 1 , wherein an encoded signal processed in quadrature mode exhibits two zeroes in the signal band.

3. The programmable delta-sigma modulator of claim 1 , wherein an encoded signal processed in low-pass mode exhibits at least one zero in the signal band and at least one zero in the image band.

4. A programmable delta-sigma modulator, comprising:
a first channel configured to receive an in-phase signal and including a first delta-sigma loop filter; and
a second channel configured to receive a quadrature signal and including a second delta-sigma loop filter;
each of the first delta-sigma loop filter and the second delta-sigma loop filter comprising:
an integrator;
a quantizer having an input coupled to an output of the integrator;
a summing node having an output coupled to an input of the integrator;
a feedforward path from an input of the delta-sigma loop filter to a first input of the summing node; and
a first feedback path from an output of the quantizer to a second input of the summing node; and

at least one cross-coupling path between the first delta-sigma loop filter and the second delta-sigma loop filter, the at least one cross-coupling path including one or more programmable coefficients for configuring the programmable delta-sigma modulator in a low-pass mode or a quadrature mode.

5. The programmable delta-sigma modulator of claim 4 , wherein each of the first delta-sigma loop filter and the second delta-sigma loop filter further comprises:
an additional summing node having a first input coupled to the input of the delta-sigma loop filter;
an additional integrator having an input coupled to an output of the additional summing node and an output coupled to a third input of the summing node; and
a second feedback path from the output of the quantizer to a second input of additional summing node.

6. The programmable delta-sigma modulator of claim 5 , further comprising:
a first path coupling an output of the first integrator of the first delta-sigma loop filter to a third input of the second summing node of the second delta-sigma loop filter;
a second path coupling an output of the first integrator of the second delta-sigma loop filter to a third input of the second summing node of the first delta-sigma loop filter;
a third path coupling an output of the additional integrator of the first delta-sigma loop filter to a fourth input of the additional summing node of the second delta-sigma loop filter; and
a fourth path coupling an output of the additional integrator of the second delta-sigma loop filter to a fourth input of the additional summing node of the first delta-sigma loop filter.

7. The programmable delta-sigma modulator of claim 6 , wherein at least one of the first path, the second path, the third path, the fourth path includes a multiplexer for switching a polarity of a coefficient of an associated path.

8. The programmable delta-sigma modulator of claim 6 , wherein:
each of the first path, the second path, the third path, and the fourth path include a programmable coefficient; and
each of the first path, the second path, the third path, and the fourth path are configured to be in one of an enabled state and a disabled state.

9. The programmable delta-sigma modulator of claim 6 , further comprising:
a fifth path coupling an output of the integrator of the first delta-sigma loop filter to a fifth input of the summing node of the first delta-sigma loop filter; and
a sixth path coupling an output of the integrator of the second delta-sigma loop filter to a fifth input of the summing node of the second delta-sigma loop filter.

10. The programmable delta-sigma modulator of claim 9 , wherein:
each of the fifth path and the sixth path include a programmable coefficient; and
each of the fifth path and the sixth path are configured to be in one of an enabled state and a disabled state.

11. The programmable delta-sigma modulator of claim 6 , further comprising:
a fifth path coupling an input of first delta-sigma loop filter to a fifth input of the summing node of the second delta-sigma loop filter; and
a sixth path coupling an input of second delta-sigma loop filter to a fifth input of the summing node of the first delta-sigma loop filter.

12. The programmable delta-sigma modulator of claim 11 , further comprising:
a seventh path coupling an output of the additional integrator of first delta-sigma loop filter to a fourth input of the additional summing node of the first delta-sigma loop filter;
an eighth path coupling an output of the integrator of first delta-sigma loop filter to a sixth input of the summing node of the first delta-sigma loop filter;
a ninth path coupling an output of the additional integrator of second delta-sigma loop filter to a fourth input of the additional summing node of the second delta-sigma loop filter; and
a tenth path coupling an output of the integrator of second delta-sigma loop filter to a sixth input of the summing node of the second delta-sigma loop filter.

13. A programmable receiver, comprising:
an analog module comprising a programmable delta-sigma analog-to-digital converter (ADC), the delta-sigma ADC comprising:
first and second channels, each of the first and second channels including a loop filter;
at least one first cross coupling path coupling the first channel to the second channel; and
at least one second cross coupling path coupling the second channel to the first channel, each of the at least one first cross coupling path and the at least one second cross coupling path including a programmable coefficient and a multiplexer for switching a polarity of the programmable coefficient; and

a digital module including a digital filter coupled to an output of the delta-sigma ADC.

14. The programmable receiver of claim 13 , wherein each of the first channel and the second channel include:
a first integrator;
a first summing node having a first input coupled to an input of the channel and an output coupled to an input of the first integrator;
a second summing node having a first input coupled to an output of the first integrator;
a second integrator having an input coupled to an output of the second summing node;
a quantizer having an input coupled to an output of the second integrator;
an input-feedforward path from the input of the channel to a second input of the second summing node;
a first feedback path from an output of the quantizer to a third input of the second summing node; and
a second feedback path from the output of the quantizer to a second input of the first summing

Assignees

• Microchip Tech Inc

Inventors

• Rajaee Omid
• Bagheri Rahim
• Pourbagheri Saeed
• Mehrjoo Mohammad
• Bagheri Mahdi
• Chiem Edwin
• Wang Jun

Classifications

• H04B1/38

  Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving · CPC title

• H03M3/452 Primary

  with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input · CPC title

• H03H2017/0245

  Measures to reduce power consumption · CPC title

• H03H17/0411

  using DELTA modulation · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title