Integrated circuits with resistor structures formed from mim capacitor material and methods for fabricating same

Patent metadata

Field	Value
Publication number	US-2016126239-A1
Application number	US-201514928272-A
Country	US
Kind code	A1
Filing date	Oct 30, 2015
Priority date	Oct 30, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.

First claim

What is claimed is:

1 . A method for fabricating an integrated circuit, the method comprising:
providing a semiconductor substrate with a resistor area and a capacitor area; depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate; forming a resistor structure from the capacitor material in the resistor area; and forming electrical connections to the resistor structure in the resistor area.

2 . The method of claim 1 further comprising forming a metal-insulator-metal (MIM) capacitor in the capacitor area, wherein the MIM capacitor comprises a first conductive layer, an insulator layer formed on the first conductive layer, and a second conductive layer formed on the insulator layer, and wherein the first conductive layer is formed from the capacitor material.

3 . The method of claim 1 further comprising forming a metal-insulator-metal (MIM) capacitor in the capacitor area, wherein the MIM capacitor comprises a first conductive layer, an insulator layer formed on the first conductive layer, and a second conductive layer formed on the insulator layer, and wherein the second conductive layer is formed from the capacitor material.

4 . The method of claim 1 further comprising forming a resistor shield around the resistor structure in the resistor area.

5 . The method of claim 1 wherein forming the resistor structure from the capacitor material in the resistor area comprises:
etching the capacitor material to form distinct resistor segments;
depositing an insulator layer over the distinct resistor segments; and
depositing a second capacitor material over the insulator layer.

6 . The method of claim 1 wherein forming the resistor structure from the capacitor material in the resistor area comprises:
depositing an insulator layer over the capacitor material;
depositing a second capacitor material over the insulator layer; and
etching the second capacitor material to form upper distinct resistor segments.

7 . The method of claim 1 wherein forming the resistor structure from the capacitor material in the resistor area comprises:
etching the capacitor material to form lower distinct resistor segments;
depositing an insulator layer over the lower distinct resistor segments;
depositing a second capacitor material over the insulator layer; and
etching the second capacitor material to form upper distinct resistor segments aligned with the lower distinct resistor segments.

8 . The method of claim 7 further comprising electrically connecting selected lower distinct resistor segments in series.

9 . The method of claim 7 wherein further comprising electrically connecting selected lower distinct resistor segments and selected upper distinct resistor segments in series.

10 . The method of claim 7 wherein further comprising electrically connecting selected lower distinct resistor segments and selected upper distinct resistor segments in parallel.

11 . The method of claim 1 wherein forming the resistor structure from the capacitor material in the resistor area comprises forming an active resistor structure from the capacitor material in the resistor area and forming a dummy resistor structure from the capacitor material in the resistor area.

12 . A method for fabricating an integrated circuit, the method comprising:
depositing a dielectric layer overlying a resistor area and a capacitor area of a semiconductor substrate; depositing a capacitor material over the dielectric layer overlying the resistor area and the capacitor area of the semiconductor substrate; patterning a mask overlying the capacitor material to selectively define masked regions of the capacitor material overlying the resistor area and the capacitor areas and to define unmasked regions of the capacitor material; removing the unmasked regions of the capacitor material; and forming a resistor structure from the capacitor material in the resistor area.

13 . The method of claim 12 further comprising forming a capacitor from the capacitor material in the capacitor area.

14 . The method of claim 12 wherein forming the resistor structure from the capacitor material in the resistor area comprises:
etching the capacitor material to form distinct resistor segments; and
electrically connecting selected distinct resistor segments.

15 . The method of claim 14 further comprising forming electrical connections to the resistor structure in the resistor area.

16 . The method of claim 12 wherein depositing the capacitor material over the dielectric layer overlying the resistor area and the capacitor area of the semiconductor substrate comprises depositing a metal-insulator-metal capacitor conductive layer over the dielectric layer.

17 . The method of claim 16 further comprising depositing a metal-insulator-metal capacitor insulator layer over the metal-insulator-metal capacitor conductive layer overlying the resistor area and the capacitor area of the semiconductor substrate.

18 . An integrated circuit comprising:
a semiconductor substrate with a resistor area and a capacitor area; a metal-insulator-metal (MIM) capacitor formed in the capacitor area from a first MIM conductive layer, a MIM insulator layer, and a second MIM conductive layer; and a resistor structure formed from the first MIM conductive layer in the resistor area.

19 . The integrated circuit of claim 18 wherein the resistor structure is formed from the second conductive layer in the resistor area.

20 . The integrated circuit of claim 18 wherein the resistor structure is formed from segments of the first conductive layer in the resistor area selectively electrically connected.

Assignees

• Globalfoundries Inc

Inventors

• Singh Jagar
• Chu Sanford

Classifications

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10D84/206 Primary

  of combinations of capacitors and resistors · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title

• H01L28/40

  Electricity · mapped topic