Chip packaging method

Patent metadata

Field	Value
Publication number	US-10756077-B2
Application number	US-201715842808-A
Country	US
Kind code	B2
Filing date	Dec 14, 2017
Priority date	Nov 9, 2017
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A chip packaging method includes followings steps. A plurality of first chips are disposed on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are disposed on the first active surface. A second active surface of a second chip is electrically connected to the first active surfaces of the first chips through a plurality of second conductive pillars. An encapsulated material is formed, wherein the encapsulated material covers the plurality of first chips, the plurality of first conductive pillars, the second chip and the plurality of second conductive pillars. The encapsulated material is partially removed to expose each of the plurality of first conductive pillars. A redistribution structure is formed on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars.

First claim

What is claimed is:

1. A chip packaging method, comprising:
disposing a plurality of first chips on a carrier, wherein each of the first chips has a first active surface, and a plurality of first conductive pillars are directly disposed on the first active surface;
electrically connecting a second active surface of a second chip to each of the first active surfaces of each of the plurality of first chips directly through a plurality of second conductive pillars;
forming an encapsulated material, the encapsulated material covering the first chips, the first conductive pillars, the second chip and the second conductive pillars;
disposing a supporting structure on the carrier before forming the encapsulated material, wherein the supporting structure surrounds the first chips, and, after forming the encapsulated material, the encapsulated material covers the supporting structure;
partially removing the encapsulated material to expose each of the first conductive pillars; and
forming a redistribution structure on the encapsulated material, wherein the redistribution structure connects with the first conductive pillars,
wherein a distribution density of the second conductive pillars is greater than a distribution density of the first conductive pillars.

2. The chip packaging method as recited in claim 1 , wherein an orthographic projection area of the second conductive pillars on the first chips is less than or equal to an orthographic projection area of the first conductive pillars on the first chips.

3. The chip packaging method as recited in claim 1 , wherein a height of the second conductive pillars with respect to the first active surface is less than or equal to a height of the first conductive pillars with respect to the first active surface.

4. The chip packaging method as recited in claim 1 , wherein the first chips are electrically connected to each other through the redistribution structure.

5. The chip packaging method as recited in claim 1 , wherein, after partially removing the encapsulated material, the encapsulated material is kept to cover the second chip.

6. The chip packaging method as recited in claim 1 , further comprising:
removing the carrier after forming the redistribution structure.

7. The chip packaging method as recited in claim 1 , further comprising:
removing the carrier after forming the redistribution structure; and
cutting the supporting structure after removing the carrier, wherein the supporting structure is exposed at one side of the encapsulated material.

8. The chip packaging method as recited in claim 1 , further comprising:
cutting the supporting structure after removing the carrier, wherein the supporting structure is exposed at one side of the encapsulated material and one side of the carrier.

9. The chip packaging method as recited in claim 1 , further comprising:
keeping the carrier to serve as a heat dissipation element after forming the redistribution structure.

10. The chip packaging method as recited in claim 1 , wherein the redistribution structure comprises a plurality of patterned conductive layers, a plurality of dielectric layers, and a plurality of conductive vias, the dielectric layers and the patterned conductive layers are alternately stacked to one another, and each of the conductive vias is located in the corresponding dielectric layer and electrically connected to the corresponding patterned conductive layers.

11. The chip packaging method as recited in claim 1 , further comprising:
after forming the redistribution structure, forming a conductive contact on each of a plurality of redistribution pads of the redistribution structure.

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Chang Wen-Yuan
• Hsu Yeh-Chi
• Lu Hsueh-Chung Shelton
• Chen Wei-Cheng

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/874

  On different surfaces · CPC title