Semiconductor package and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-10032748-B2
Application number	US-201715594313-A
Country	US
Kind code	B2
Filing date	May 12, 2017
Priority date	Jan 27, 2016
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.

First claim

What is claimed is:

1. An electronic device comprising:
a signal distribution structure (SDS) having an upper SDS side and a lower SDS side, and comprising:
an SDS dielectric layer;
a first SDS conductor; and
a second SDS conductor;

a connect die (CD) comprising:
a top CD side comprising a first CD interconnection structure, and a second CD interconnection structure electrically coupled to the first CD interconnection structure; and
a bottom CD side coupled to the upper SDS side;

a first semiconductor die (SD1) comprising:
a first SD1 interconnection structure coupled to the first CD interconnection structure; and
a second SD1 interconnection structure coupled to the first SDS conductor; and

a second semiconductor die (SD2) comprising:
a first SD2 interconnection structure coupled to the second CD interconnection structure; and
a second SD2 interconnection structure coupled to the second SDS conductor.

2. The electronic device of claim 1 , wherein the entire upper SDS side is in a same plane.

3. The electronic device of claim 1 , comprising a layer of a single continuous dielectric material that laterally surrounds and vertically covers the connect die.

4. The electronic device of claim 1 , comprising:
a first dielectric layer that directly contacts and covers the connect die; and
a second dielectric layer that directly contacts and covers the signal distribution structure.

5. The electronic device of claim 1 , comprising a layer of a single continuous dielectric material that covers the upper SDS side, and comprises:
a first portion positioned directly vertically between the connect die and the first semiconductor die;
a second portion positioned directly vertically between the connect die and the second semiconductor die;
a third portion positioned directly vertically between the signal distribution structure and the first semiconductor die, but not directly vertically between the connect die and the first semiconductor die;
a fourth portion positioned directly vertically between the signal distribution structure and the second semiconductor die, but not directly vertically between the connect die and the second semiconductor die;
a fifth portion that covers a top side of the first semiconductor die; and
a sixth portion that covers a top side of the second semiconductor die.

6. The electronic device of claim 1 , comprising a conductive layer coupled to the bottom CD side and to the upper SDS side.

7. The electronic device of claim 1 , wherein a first vertical distance between a lower side of the first semiconductor die and the upper CD side is different from a second vertical distance between the lower side of the first semiconductor die and the upper SDS side.

8. The electronic device of claim 1 , wherein the first SD1 interconnection structure comprises a first metal pillar; and the second SD1 interconnection structure comprises a second metal pillar that is at least two times wider than the first metal pillar.

9. The electronic device of claim 1 , wherein the connect die comprises:
a semiconductor substrate;
a conductive layer on the semiconductor substrate; and
an inorganic dielectric layer on the conductive layer and comprising:
a first aperture through which a first portion of the conductive layer is exposed; and
a second aperture through which a second portion of the conductive layer is exposed,

wherein the first CD interconnection structure is electrically connected to the first portion of the conductive layer through the first aperture, and the second CD interconnection structure is electrically connected to the second portion of the conductive layer through the second aperture.

10. The electronic device of claim 1 , wherein the signal distribution structure comprises a substrate that comprises ceramic and/or glass.

11. The electronic device of claim 1 , wherein:
the first SD1 interconnection structure is directly connected to the first CD interconnection structure;
the second SD1 interconnection structure is directly connected to the first SDS conductor;
the first SD2 interconnection structure is directly connected to the second CD interconnection structure; and
the second SD2 interconnection structure is directly connected to the second SDS conductor.

12. An electronic device comprising:
a signal distribution structure (SDS) comprising: an SDS dielectric layer, a first SDS conductor, a second SDS conductor, and a third SDS conductor;
a first connect die (CD1) comprising:
a top CD1 side comprising a first CD1 interconnection structure and a second CD1 interconnection structure electrically coupled to the first CD1 interconnection structure; and
a bottom CD1 side coupled to an upper side of the signal distribution structure;

a second connect die (CD2) comprising:
a top CD2 side comprising a first CD2 interconnection structure and a second CD2 interconnection structure electrically coupled to the first CD2 interconnection structure; and
a bottom CD2 side coupled to the upper side of the signal distribution structure;

a first semiconductor die (SD1) comprising:
a first SD1 interconnection structure coupled to the first CD1 interconnection structure;
a second SD1 interconnection structure coupled to the first SDS conductor; and
a third SD1 interconnection structure coupled to the first CD2 interconnection structure;

a second semiconductor die (SD2) comprising:
a first SD2 interconnection structure coupled to the second CD1 interconnection structure; and
a second SD2 interconnection structure coupled to the second SDS conductor; and

a third semiconductor die (SD3) comprising:
a first SD3 interconnection structure coupled to the second CD2 interconnection structure; and
a second SD3 interconnection structure coupled to the third SDS conductor.

13. The electronic device of claim 12 , wherein:
the first connect die and the second semiconductor die are positioned toward a first lateral side of the first semiconductor die; and
the second connect die and the third semiconductor die are positioned toward a second lateral side, opposite the first lateral side, of the first semiconductor die.

14. The electronic device of claim 12 , wherein:
the first semiconductor die comprises a processor die;
the second semiconductor die comprises a first memory die; and
the third semiconductor die comprises a second memory die.

15. The electronic device of claim 12 , comprising a layer of a single continuous dielectric material that laterally surrounds and vertically covers the first connect die, the second connect die, the first semiconductor die, the second semiconductor die, and the third semiconductor die.

16. A method for manufacturing an electronic device, the method comprising:
providing a connect die (CD) coupled to a signal distribution structure (SDS), wherein:
the signal distribution structure has an upper SDS side and a lower SDS side, and comprises:
an SDS dielectric layer;
a first SDS conductor; and
a second SDS conductor; and

the connect die has an upper CD side, and a lower CD side coupled to the upper SDS side, and comprises:
a first CD interconnection structure on the upper CD side; and
a second CD interconnection structure on the upper CD side and electrically coupled to the first CD interconnection structure;

providing a first semiconductor die (SD1) coupled to the signal distribution structure and coupled to the connect die, wherein the first semiconductor die comprises:
a first SD1 interconnection structure coupled to the first CD interconnection structure; and
a second SD1 int

Assignees

• Amkor Technology Inc

Inventors

• Hiner David
• Kelly Michael
• Huemoeller Ronald

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title