Method of manufacturing integrated fan-out package

Patent metadata

Field	Value
Publication number	US-10756052-B2
Application number	US-201916524146-A
Country	US
Kind code	B2
Filing date	Jul 28, 2019
Priority date	May 17, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

First claim

What is claimed is:

1. A method of manufacturing an integrated fan-out (InFO) package, comprising:
forming a package array;
providing a dielectric layer having a core layer formed thereon, wherein the core layer comprises a plurality of cavities penetrating through the core layer;
attaching the dielectric layer and the core layer onto the package array such that the core layer is located between the dielectric layer and the package array; and
forming a plurality of first conductive patches on the dielectric layer above the plurality of cavities.

2. The method according to claim 1 , further comprising:
singulating the package array, the dielectric layer, and the core layer.

3. The method according to claim 1 , wherein the step of forming the package array comprises:
providing a first redistribution structure;
forming a plurality of through interlayer vias (TIV) and a plurality of dies over the first redistribution structure;
forming an encapsulant encapsulating the plurality of dies and the plurality of TIVs;
forming a second redistribution structure over the plurality of dies, the plurality of TIVs, and the encapsulant;
forming an insulating layer over the first redistribution structure opposite to the plurality of dies.

4. The method according to claim 3 , wherein the step of forming the package array further comprises:
forming a plurality of second conductive patches over the insulating layer, wherein the plurality of second conductive patches are located inside of the plurality of cavities of the core layer.

5. The method according to claim 1 , further comprising:
forming a vent in the dielectric layer.

6. The method according to claim 5 , wherein a vertical projection of the vent onto the package array is overlapped with a vertical projection of one of the plurality of cavities onto the package array.

7. The method according to claim 1 , further comprising:
forming a vent in the core layer.

8. A method of manufacturing an integrated fan-out (InFO) package, comprising:
forming a package array;
placing a plurality of core patterns on the package array, wherein each of the plurality of core patterns comprises a plurality of cavities, and the plurality of core patterns are spaced apart from each other;
forming a dielectric layer on the plurality of core patterns;
forming a plurality of first conductive patches on the dielectric layer, wherein the plurality of first conductive patches are arranged corresponding to the plurality of cavities.

9. The method according to claim 8 , wherein the dielectric layer comprises a plurality of discontinuous segments, and each discontinuous segment is formed on the corresponding core pattern such that sidewalls of each discontinuous segment are substantially aligned with sidewalls of the corresponding core pattern.

10. The method according to claim 8 , further comprising:
singulating the package array.

11. The method according to claim 8 , wherein the plurality of cavities of the plurality of core patterns are formed by a punching process or a photolithography process.

12. The method according to claim 8 , wherein the plurality of core patterns are placed on the package array through a pick-and-place process.

13. The method according to claim 8 , wherein the step of forming the package array comprises:
providing a carrier;
forming a first redistribution structure over the carrier;
forming a plurality of through interlayer vias (TIV) and a plurality of dies over the first redistribution structure;
forming an encapsulant encapsulating the plurality of dies and the plurality of TIVs;
forming a second redistribution structure over the plurality of dies, the plurality of TIVs, and the encapsulant;
forming an insulating layer over the first redistribution structure opposite to the plurality of dies.

14. The method according to claim 13 , wherein the step of forming the package array further comprises:
forming a plurality of second conductive patches over the insulating layer, wherein the plurality of second conductive patches are located inside of the plurality of cavities of the plurality of core patterns.

15. The method according to claim 8 , further comprising:
forming a vent in each of the plurality of core patterns; and
forming a vent in the dielectric layer.

16. A method of manufacturing an integrated fan-out (InFO) package, comprising:
forming a package array;
forming a core layer having a plurality of cavities over the package array;
forming a dielectric layer on the core layer;
attaching the dielectric layer to an adhesive layer;
attaching a plurality of first conductive patches to the adhesive layer, wherein the plurality of first conductive patches are arranged corresponding to the plurality of cavities.

17. The method according to claim 16 , wherein the step of attaching the plurality of first conductive patches to the adhesive layer precedes the step of attaching the dielectric layer to the adhesive layer.

18. The method according to claim 16 , wherein the step of attaching the dielectric layer to the adhesive layer precedes the step of attaching the plurality of first conductive patches to the adhesive layer.

19. The method according to claim 16 , wherein the step of attaching the dielectric layer to the adhesive layer and the step of attaching the plurality of first conductive patches to the adhesive layer comprises:
placing a conductive foil on a carrier film;
forming the adhesive layer on the conductive foil
punching the conductive foil and the adhesive layer to remove a portion of the conductive foil and a portion of the adhesive layer to form the plurality of first conductive patches attached to the adhesive layer;
attaching the adhesive layer, the plurality of first conductive patches, and the carrier film onto the dielectric layer such that the adhesive layer and the plurality of first conductive patches are located between the carrier film and the dielectric layer; and
removing the carrier film from the plurality of first conductive patches.

20. The method according to claim 16 , wherein the step of attaching the plurality of first conductive patches to the adhesive layer comprises:
providing a stencil over the adhesive layer, wherein the stencil comprises a plurality of apertures exposing the adhesive layer;
distributing the plurality of first conductive patches over the stencil; and
vibrating the plurality of first conductive patches such that the plurality of first conductive patches are driven into the plurality of apertures of the stencil.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wan Albert
• Hsieh Ching-Hua
• Tsai Chung-Hao
• Wang Chuei-Tang
• Shih Chao-Wen
• Pu Han-Ping
• Hwang Chien-Ling
• Lee Pei-Hsuan
• Tang Tzu-Chun
• Chiu Yu-Ting
• Kuo Jui-Chang

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W44/248

  for antennas · CPC title