Packaged semiconductor system having unidirectional connections to discrete components

Patent metadata

Field	Value
Publication number	US-10756013-B2
Application number	US-202016792619-A
Country	US
Kind code	B2
Filing date	Feb 17, 2020
Priority date	Nov 8, 2017
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A packaged semiconductor system, including: at least one electronic device on a device mounting surface of a substrate having terminals for attaching bond wires; at least one discrete component adjacent to the at least one electronic device, a second electrode of the at least one discrete component parallel to and spaced from a first electrode by a component body; the first electrode a metal foil having a protrusion extending laterally from the body and having a surface facing towards the second electrode; bonding wires interconnecting respective terminals of the at least one electronic device, the first electrode and the second electrode, and bonded to the surface of the second electrode and to the protrusion that extend away from the respective surfaces in a same direction; and packaging compound covering portions of the at least one electronic device, the at least one discrete component, and the bonding wires.

First claim

What is claimed is:

1. A semiconductor package comprising:
a substrate;
a semiconductor die attached to, and electrically connected to the substrate; and
a capacitor including a first electrode attached to, and electrically coupled to the substrate, a second electrode electrically coupled to the semiconductor die, and a sheet of capacitive elements between the first electrode and the second electrode, and electrically coupled to the substrate;
an insulative layer covering portions of a top surface of the sheet of capacitive elements; and
molding compound covering portions of the substrate, the semiconductor die, the capacitor and the insulative layer.

2. The semiconductor package of claim 1 , wherein the insulative layer covers side walls of the sheet of capacitive elements.

3. The semiconductor package of claim 1 , wherein the sheet of capacitive elements includes metal particles covered in dielectric skins and a conductive polymeric compound filling spaces between the metal particles.

4. The semiconductor package of claim 1 , wherein the substrate includes a first substrate contact pad electrically connected to a first terminal of the semiconductor die via a first wire bond.

5. The semiconductor package of claim 1 , wherein the second electrode is electrically coupled between a second terminal of the semiconductor die to the second electrode via a second wire bond.

6. The semiconductor package of claim 1 , wherein the first electrode is electrically coupled to a second substrate contact pad of the substrate via a third wire bond.

7. The semiconductor package of claim 1 , wherein a plane along the side wall is at a right angle with respect to a plane along a surface of the first electrode.

8. The semiconductor package of claim 1 , wherein the first electrode and the second electrode are parallel to each other.

9. The semiconductor package of claim 1 , wherein the first electrode and the second electrode are metal foils.

10. The semiconductor package of claim 1 , wherein the metal particles include tantalum, and the dielectric skins of the metal particles include a tantalum oxide.

11. The semiconductor package of claim 1 further comprising at least one discrete component attached to the substrate and electrically connected to the semiconductor die.

12. The semiconductor package of claim 1 , wherein the substrate is selected from a group consisting of a conductive lead frame, flame retardant epoxy resin substrate material (FR-4), bismaleimide-triazine (BT) resin, fiberglass, polyimide, ceramic, epoxy resin, and Kapton.

13. The semiconductor package of claim 1 , wherein the contact pads of the substrate, the terminals of the semiconductor die, the second electrode and the protrusion of the first electrode are bondable surfaces including a metal layer selected from tin, nickel, palladium, silver, gold, copper, aluminum, and alloys and combinations thereof.

14. The semiconductor package of claim 1 , wherein the substrate is a portion of a lead frame.

15. A semiconductor package comprising:
a substrate;
a semiconductor die attached to, and electrically connected to the substrate; and
a capacitor on the semiconductor die, the capacitor including a first electrode attached to the semiconductor die, a second electrode electrically coupled to the semiconductor die, and a sheet of capacitive elements between the first electrode and the second electrode, and electrically coupled to the substrate;
an insulative layer covering portions of a top surface of the sheet of capacitive elements; and
molding compound covering portions of the substrate, the semiconductor die, the capacitor and the insulative layer.

16. The semiconductor package of claim 15 , wherein the first electrode is attached to the semiconductor die via a film.

17. The semiconductor package of claim 15 , wherein:
the sheet of capacitive elements includes metal particles covered in dielectric skins and a conductive polymeric compound filling spaces between the metal particles;
the substrate includes a first substrate contact pad electrically connected to a first terminal of the semiconductor die via a first wire bond;
the second electrode is electrically coupled between a second terminal of the semiconductor die to the second electrode via a second wire bond; and
the first electrode is electrically coupled to a second substrate contact pad of the substrate via a third wire bond.

18. The semiconductor package of claim 15 , wherein the first electrode extends laterally from a side wall of the sheet of capacitive elements.

19. The semiconductor package of claim 15 , wherein the insulative layer covers side walls of the sheet of capacitive elements.

Assignees

• Texas Instruments Inc

Inventors

• Gandhi Saumya
• Romig Matthew David
• Castro Abram

Classifications

• H10W90/769

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/764

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title