Control apparatus that controls memory and control method thereof

Patent metadata

Field	Value
Publication number	US-10754415-B2
Application number	US-201715416333-A
Country	US
Kind code	B2
Filing date	Jan 26, 2017
Priority date	Feb 3, 2016
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

With a method of connecting SRAMs by daisy chain connection, the power state of all the SRAMs is determined uniquely. Because of this, even in the case of an SRAM of a function module in which SRAM access does not occur, the SRAM returns to the normal mode. The control apparatus includes a plurality of function modules including a memory capable of making a transition between a first power state and a second power state that is more power-saving than the first power state in accordance with a control signal. Then, control is performed so as to output a first signal that gives instructions to make a transition of the power state based on the control signal to a memory of a function module of the plurality of function modules in which processing using a function that the function module has is performed.

First claim

What is claimed is:

1. A control apparatus comprising:
a first memory circuit that stores data, and is configured to shift from a second state to a first state according to a first predetermined signal, wherein power consumption of the second state is lower than that of the first state;
a first processing circuit operable in a first operation mode and a second operation mode, wherein in the first operation mode the first processing circuit is configured to perform a first predetermined processing for input data, to access the first memory circuit, and to output the processed input data, and wherein in the second operation mode the first processing circuit is configured to output the input data without accessing the first memory circuit;
a first storage circuit that stores a value corresponding to the operation mode of the first processing circuit; and
a first output circuit that, based on a value corresponding to the first operation mode of the first processing circuit stored in the first storage circuit, outputs the first predetermined signal to the first memory circuit, wherein the first memory circuit shifts from the second state to the first state according to the first predetermined signal from the output module first output circuit;
a second memory circuit that stores data, and is configured to shift from the second state to the first state according to a second predetermined signal;
a second processing circuit operable in a first operation mode and a second operation mode, wherein in the first operation mode the second processing circuit is configured to perform a second predetermined processing for input data from the first processing circuit, to access the second memory circuit, and to output the processed input data, and wherein in the second operation mode the second processing circuit is configured to output the input data without accessing the second memory circuit;
a second storage circuit that stores a value corresponding to the operation mode of the second processing circuit; and
a second output circuit that, based on a value corresponding to the first operation mode of the second processing circuit stored in the second storage circuit, outputs the second predetermined signal to the second memory circuit, wherein the second memory circuit shifts from the second state to the first state according to the second predetermined signal from the second output circuit, wherein
the first processing circuit outputs the processed input data to the second processing circuit in the first operation mode, and outputs the input data without performing the predetermined processing to the second processing circuit in the second operation mode.

2. The control apparatus according to claim 1 , wherein
the first output circuit outputs a timing signal to the second output circuit, wherein the second output circuit, based on the value stored in the second storage circuit, outputs the second predetermined signal to the second memory circuit when the timing signal is input.

3. The control apparatus according to claim 2 , wherein
the second processing circuit performs the second predetermined processing different from the first predetermined processing that the first processing circuit performs to the input data.

4. The control apparatus according to claim 2 , wherein
the first output circuit outputs the timing signal to the second output circuit after an output of the first predetermined signal to the first memory circuit.

5. The control apparatus according to claim 1 , further comprising:
a clock gating circuit that gates a clock signal to the first memory circuit,
wherein the first output circuit outputs a clock enable signal to the clock gating circuit after an output of the first predetermined signal.

6. The control apparatus according to claim 1 , wherein
the second state is a state where supply of power to peripheral circuits except for a memory cell array included in the first memory circuit is stopped, and
the first state is a state where power is supplied to the memory cell array and the peripheral circuits.

7. The control apparatus according to claim 6 , wherein
the first memory circuit is a SRAM (Static Random Access Memory).

8. The control apparatus according to claim 1 , wherein
the first processing circuit is a circuit that, by using the data stored in the first memory circuit, performs image processing for image data that is input.

9. The control apparatus according to claim 1 , further comprising:
a printing device configured to print an image.

10. The control apparatus according to claim 1 , wherein
the first state is a state where the data can be read from memory cell arrays of the first memory circuit, and
the second state is a state where the data cannot be read from the memory cell arrays of the first memory circuit.

11. The control apparatus according to claim 1 , wherein
the data stored in the first memory circuit is at least one of a parameter that the first processing circuit uses for processing or the input data that is input to the first processing circuit.

Assignees

• Canon Kk

Inventors

• Ozawa Manabu

Classifications

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G11C11/413 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title