Processor and memory communication in a stacked memory system
US-2024411709-A1 · Dec 12, 2024 · US
US9147441B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9147441-B2 |
| Application number | US-201313973490-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 22, 2013 |
| Priority date | Sep 26, 2012 |
| Publication date | Sep 29, 2015 |
| Grant date | Sep 29, 2015 |
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A semiconductor memory device including a plurality of memory blocks MBA0, MBA1, MBB0, MBB1; a plurality of bus lines 26 provided respectively associated with the plurality of memory blocks; a plurality of input/output ports 22 a, 22 b ; a selector 28 a, 28 b selectively connecting each of the plurality of bus lines to one of the plurality of input/output ports; and a setting unit 38 a, 38 b setting a connection of the selector.
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What is claimed is: 1. A semiconductor memory device comprising: a plurality of memory blocks; a plurality of bus lines, the plurality of bus lines being respectively associated with the plurality of memory blocks; a plurality of input/output ports; a plurality of selectors and a plurality of registers associated with the plurality of input/output ports, wherein each selector of the plurality of selectors is configured to selectively connect each of the plurality of bus line…
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