Controlling clock input buffers

Patent metadata

Field	Value
Publication number	US-9577611-B2
Application number	US-201414448706-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Dec 30, 2009
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

An integrated circuit may have a clock input pin coupled to a buffer ( 24 ). The buffer may supply a clock signal ( 28 ) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles Of the clock signal, the buffer is automatically powered up.

First claim

The invention claimed is:

1. An apparatus, comprising:
a buffer configured to receive a first clock signal and provide a second clock signal responsive to a buffer enable signal; and
a controller configured to enable the buffer responsive to detection of the first clock signal, the controller comprising:
a detector configured to count a number of cycles of the first clock signal and further configured to determine when the number of cycles of the first clock signal reaches a threshold; and
a latch coupled to the detector and configured to generate the buffer enable signal when the number of cycles of the first clock signal reaches the threshold, the latch further configured to disable the buffer responsive to transitioning to a power down state.

2. The apparatus of claim 1 , wherein the latch is further configured to disable the buffer responsive to a reset signal provided by a flip-flop.

3. The apparatus of claim 1 , wherein the buffer comprises a differential amplifier.

4. An apparatus comprising:
a buffer configured to receive a first clock signal and provide a second clock signal responsive to an enable signal; and
a controller configured to enable the buffer responsive to detection of the first clock signal, the controller comprising:
a detector configured to count a number of cycles of the first clock signal and further configured to determine when the number of cycles of the first clock signal reaches a threshold;
a latch coupled to the detector and configured to generate the enable signal when the number of cycles of the first clock signal reaches the threshold; and
a flip-flop configured to receive the second clock signal and provide a second enable signal to a plurality of input buffers based on a clock enable signal and the second clock signal.

5. An apparatus comprising:
a buffer configured to receive a first clock signal and provide a second clock signal responsive to an enable signal; and
a controller configured to enable the buffer responsive to detection of the first clock signal, the controller comprising:
a detector configured to count a number of cycles of the first clock signal and further configured to determine when the number of cycles of the first clock signal reaches a threshold;
a latch coupled to the detector and configured to generate the enable signal when the number of cycles of the first clock signal reaches the threshold; and
a flip-flop configured to receive the second clock signal and coupled to the latch, the flip-flop further configured to reset the latch based at least in part on a clock enable signal transitioning to a low logic state.

6. The apparatus of claim 5 , further comprising a falling edge detector configured to detect a falling edge of the output of the flip-flop, the flip-flop further configured to reset the latch based at least in part on the detection of the falling edge of the output of the flip-flop.

7. An apparatus comprising:
a clock detector circuit configured to detect a number of cycles of an input clock signal received by a clock input buffer;
a clock buffer enable circuit configured to provide an enable signal to the clock input buffer based on a number of clock cycles detected by the clock detector circuit reaching a threshold; and
an input buffer enable circuit configured to enable a plurality of data input buffers based on a clock enable signal and a clock signal provided by the clock input buffer,
wherein the clock signal provided by the clock input buffer is enabled before receipt of a clock enable signal.

8. The apparatus of claim 7 , wherein the clock buffer enable circuit comprises a latch coupled to the clock detector circuit and configured to provide the enable signal to the clock input buffer responsive to the clock detector circuit detecting a threshold number of clock cycles.

9. The apparatus of claim 8 , wherein the latch is further configured to disable the clock input buffer based on a reset signal provided by a flip-flop.

10. The apparatus of claim 7 , wherein a latch circuit is configured to provide a reset signal responsive to transitioning to a power down state.

11. The apparatus of claim 7 , wherein the threshold is two clock cycles.

Assignees

• Micron Technology Inc

Inventors

• Balluchi Daniele
• Vimercati Daniele
• Mirichigni Graziano

Classifications

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C11/4072 Primary

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C7/225

  Clock input buffers · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title