Apparatus for overload recovery of an integrator in a sigma-delta modulator

Patent metadata

Field	Value
Publication number	US-10749544-B2
Application number	US-201916457058-A
Country	US
Kind code	B2
Filing date	Jun 28, 2019
Priority date	Jun 25, 2015
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

Described is an apparatus which comprises: a first integrator to receive an input signal and to generate a first output; a second integrator to receive the first output or a version of the first output and to generate a second output; and an analog-to-digital converter (ADC) to quantize the second output into a digital representation, the ADC including a detection circuit to detect an overload condition in the second output.

First claim

We claim:

1. An apparatus, comprising:
a first integrator configured to receive an input signal and to generate a first output signal;
a second integrator configured to receive the first output signal or a version of the first output signal and to generate a second output signal;
an analog-to-digital converter (ADC) configured to quantize the second output signal into a digital representation;
logic configured to detect whether the second output signal is saturated at a first voltage level or a second voltage level for at least two consecutive cycles; and
circuitry configured to adjust a current at the first integrator, without bypassing the first integrator, responsive to the logic detecting that the second output signal is saturated at a first voltage level or the second voltage level for the at least two consecutive cycles.

2. The apparatus of claim 1 , further comprising:
a digital-to-analog converter (DAC) coupled to an input of the first integrator.

3. The apparatus of claim 1 , wherein the logic comprises registers.

4. The apparatus of claim 1 , wherein the first and second integrators are differential integrators.

5. The apparatus of claim 1 , further comprising:
a first digital-to-analog converter (DAC) coupled to an input of the first integrator; and
a second DAC coupled to an output of the first integrator.

6. The apparatus of claim 5 , wherein the second DAC is configured to provide an analog signal, which is combined with the first output signal from the first integrator, and wherein the second DAC is configured to adjust a signal attribute of the second output signal according to the digital representation.

7. The apparatus of claim 1 , wherein the ADC comprises a successive approximation (SAR) quantizer.

8. The apparatus of claim 1 , wherein the ADC comprises a sigma-delta converter.

9. The apparatus of claim 1 , wherein the first voltage level is substantially a power supply voltage level, and wherein the second voltage level is substantially a ground voltage level.

10. A multi-order sigma-delta (SD) analog-to-digital converter (ADC), comprising:
a first integrator and a second integrator, wherein the first integrator is configured to receive an input signal and to generate a first output signal, and wherein the second integrator is configured to receive the first output signal or a version of the first output signal and to generate a second output signal;
a quantizer configured to quantize the second output signal into a digital representation;
logic configured to detect whether the second output signal is saturated at a first voltage level or a second voltage level for at least two consecutive cycles; and
circuitry configured to reduce a current at an output of the first integrator in response to the logic detecting that the second output signal is saturated at the first voltage level or the second voltage level for the at least two consecutive cycles.

11. The multi-order SD ADC of claim 10 , wherein the first voltage level is substantially a power supply voltage level, and wherein the second voltage level is substantially a ground voltage level.

12. The multi-order SD ADC of claim 10 , wherein the quantizer comprises a successive approximation (SAR) quantizer.

13. The multi-order SD ADC of claim 10 , wherein the logic comprises registers.

14. The multi-order SD ADC of claim 10 , wherein the first and second integrators are differential integrators.

15. An apparatus, comprising:
a first integrator configured to receive an input signal and to generate a first output signal;
a second integrator configured to receive the first output signal or a version of the first output signal and to generate a second output signal;
an analog-to-digital converter (ADC) configured to quantize the second output signal into a digital representation;
logic configured to detect whether the second output signal is stuck at a level for at least two consecutive cycles; and
circuitry configured to adjust a current at the first integrator in response to the logic detecting that the second output signal is stuck at the level for the at least two consecutive cycles.

16. The apparatus of claim 15 , comprising:
a digital-to-analog converter (DAC) coupled to an input of the first integrator.

17. The apparatus of claim 15 , wherein the logic comprises registers.

18. The apparatus of claim 15 , wherein the first and second integrators are differential integrators.

19. The apparatus of claim 15 , comprising:
a first digital-to-analog converter (DAC) coupled to an input of the first integrator; and
a second DAC coupled to an output of the first integrator.

20. The apparatus of claim 19 , wherein the second DAC is configured to provide an analog signal, which is combined with the first output signal from the first integrator, and wherein the second DAC is configured to adjust a signal attribute of the second output signal according to the digital representation.

21. The apparatus of claim 15 , wherein the ADC comprises a successive approximation (SAR) quantizer.

22. An apparatus comprising:
a loop filter having at least two integrators;
an analog-to-digital converter (ADC) configured to quantize an output signal of the loop filter into a digital representation;
logic to detect whether the output signal of the loop filter is saturated at a first voltage level or a second voltage level for at least two consecutive cycles; and
circuitry to adjust a current at the output of the loop filter, without bypassing a first integrator of the at least two integrators, in response to the logic detecting that the output signal of the loop filter is saturated at the first voltage level or the second voltage level for the at least two consecutive cycles.

23. The apparatus of claim 22 , further comprising:
at least two digital-to-analog converters (DACs) at least one of which is coupled to the ADC.

24. The apparatus of claim 22 , wherein the logic comprises registers.

25. The apparatus of claim 22 , wherein the at least two integrators are differential integrators.

26. The apparatus of claim 22 , wherein the ADC comprises a successive approximation (SAR) quantizer.

27. The apparatus of claim 22 , wherein the ADC comprises a sigma-delta converter.

Assignees

• Apple Inc

Inventors

• Kauffman John G
• Dufrene Krzysztof

Classifications

• H03M3/444 Primary

  using non-linear elements, e.g. limiters · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/10

  Calibration or testing · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title