Frequency selective circuit configured to convert an analog input signal to a digital output signal

Patent metadata

Field	Value
Publication number	US-9543978-B2
Application number	US-201314769164-A
Country	US
Kind code	B2
Filing date	Feb 21, 2013
Priority date	Feb 21, 2013
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A frequency selective circuit configured to convert an analog input signal to a digital output signal comprises an analog-to-digital converter ( 44 ) to generate the digital output signal of the circuit based on an analog input signal to the analog-to-digital converter ( 44 ); a digital-to-analog converter ( 46, 47 ) to generate an analog feedback signal based on the digital output signal from the analog-to-digital converter ( 44 ), and an analog filter arranged to generate the analog input signal to the analog-to-digital converter based on the analog feedback signal and an analog input signal to the circuit. The analog filter comprises at least two integrators ( 41, 42 ) in series, each having a feedback path comprising the analog-to-digital converter ( 44 ) in cascade with a digital-to-analog converter ( 46, 47 ), so that the overall noise transfer function of the circuit has at least two zeros in addition to zeros in the noise transfer function of the analog-to-digital converter.

First claim

The invention claimed is:

1. A frequency selective circuit configured to convert an analog input signal to a digital output signal, comprising:
an analog-to-digital converter configured to generate the digital output signal of the frequency selective circuit based on an analog input signal to the analog-to-digital converter;
a digital-to-analog converter arranged to generate an analog feedback signal based on the digital output signal generated by the analog-to-digital converter;
an analog filter arranged to generate the analog input signal to the analog-to-digital converter based on the analog feedback signal generated by the digital-to-analog converter and an analog input signal to the frequency selective circuit, wherein the analog filter comprises at least two integrators in series, each integrator having a feedback path comprising the analog-to-digital converter in cascade with a digital-to-analog converter, so that the overall noise transfer function of the frequency selective circuit has at least two zeros in addition to zeros in the noise transfer function of the analog-to-digital converter; and
a resistor arranged to form a resonator loop around two integrators of the analog filter.

2. The circuit of claim 1 , wherein each integrator of the analog filter is configured to provide a low pass filtering function having a cut-off frequency corresponding to a selected frequency band of the analog input signal to the frequency selective circuit.

3. The circuit of claim 2 , wherein the analog-to-digital converter is configured to generate the digital output signal at a sampling rate that is significantly higher than the cut-off frequency of the integrators of the analog filter.

4. The circuit of claim 1 , wherein the analog filter has a gain larger than unity.

5. The circuit of claim 1 , wherein each integrator of the analog filter has a separate feedback path comprising a digital-to-analog converter arranged to generate an analog feedback signal to the input of that integrator.

6. The circuit of claim 1 , wherein the circuit is configured to have a substantially flat signal transfer function in the pass band of the analog filter.

7. The circuit of claim 1 , wherein each integrator of the analog filter comprises an operational amplifier, a capacitor coupled between the output and an input of the operational amplifier and an input resistor coupled to said input of the operational amplifier.

8. The circuit of claim 1 wherein the analog-to-digital converter is a quantizer.

9. The circuit of claim 1 , wherein the analog-to-digital converter is a Delta-Sigma converter.

10. The circuit of claim 9 , wherein the analog-to-digital converter is a higher order Delta-Sigma converter.

11. The circuit of claim 9 , wherein the analog-to-digital converter has a discrete-time loop filter.

12. The circuit of claim 9 , wherein the analog-to-digital converter has a continuous-time loop filter.

13. The circuit of claim 9 , wherein the analog-to-digital converter comprises a cascade of integrators with feedforward compensation.

14. The circuit of claim 12 , further comprising a resistor coupled in series with the capacitor and coupled between the output and an input of the operational amplifier of at least one of the integrators of the analog filter or of the loop filter of the analog-to-digital converter.

15. The circuit of claim 1 , wherein the circuit is further configured with a zero inserted in the feedback path from the digital-to-analog converter to the analog filter.

16. The circuit of claim 15 , wherein the zero is implemented by modifying the feedback coefficients of the analog filter and introducing a direct path from the output of the digital-to-analog converter to the output of the analog filter.

17. The circuit of claim 15 , wherein the analog-to-digital converter is a Delta-Sigma converter and the zero is implemented by modified feedback coefficients of both the analog filter and the Delta-Sigma converter.

Assignees

• Ericsson Telefon Ab L M
• ERICSSON TELEFON AB L M (publ)

Inventors

• Mattisson Sven
• Anderson Martin
• Andreani Pietro
• Palm Mattias

Classifications

• H03M3/368

  of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators · CPC title

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/344 Primary

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title