Integrated wafer-level processing system

Patent metadata

Field	Value
Publication number	US-10748877-B2
Application number	US-201916369390-A
Country	US
Kind code	B2
Filing date	Mar 29, 2019
Priority date	May 2, 2016
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

First claim

What is claimed is:

1. An integrated wafer-level processing system comprising:
a memory wafer; and
a processing element connected to the memory wafer via a data connection, wherein the data connection is disposed between the processing element and the memory wafer only near one peripheral area of the processing element, remaining peripheral areas of the processing element being free of data connections.

2. The integrated wafer-level processing system of claim 1 , wherein the memory wafer comprises a plurality of memory elements.

3. The integrated wafer-level processing system of claim 2 , wherein the plurality of memory elements comprise a plurality of dynamic random access memory elements.

4. The integrated wafer-level processing system of claim 2 , wherein the plurality of memory elements comprise a plurality of flash memory elements.

5. The integrated wafer-level processing system of claim 1 , further comprising:
an interposer to provide integrated decoupling for power distribution to the memory wafer and the processing element.

6. The integrated wafer-level processing system of claim 1 , wherein the memory wafer comprises a wiring interconnect to enable the processing element to connect to the memory wafer via the data connection.

7. The integrated wafer-level processing system of claim 1 , wherein the data connection is selected from the group consisting of an electrical connection and an optical connection.

8. The integrated wafer-level processing system of claim 1 , further comprising:
a cooling unit, wherein the cooling unit is selected from the group consisting of an air cooling unit, a heat pipe, a heat spreader, heat fins, and a liquid cooling unit.

9. The integrated wafer-level processing system of claim 1 , further comprising:
a dicing channel.

10. An integrated wafer-level processing system comprising:
a plurality of memory wafers connected together; and
a processing element connected to at least one of the plurality of memory wafers via a data connection, wherein the data connection is disposed between the processing element and the memory wafer only near one peripheral area of the processing element, remaining peripheral areas of the processing element being free of data connections.

11. The integrated wafer-level processing system of claim 10 , wherein a first memory wafer of the plurality of memory wafers is stacked on top of a second memory wafer of the plurality of memory wafers.

12. The integrated wafer-level processing system of claim 11 , wherein the first memory wafer is connected to the second memory wafer via a through silicon via.

13. The integrated wafer-level processing system of claim 10 , wherein each of the plurality of memory wafers comprises a dicing channel.

14. The integrated wafer-level processing system of claim 13 , wherein the dicing channel is used for at least one of a through silicon electrical via to connect a first memory wafer of the plurality of memory wafers to a second memory wafer of the plurality of memory wafers.

15. The integrated wafer-level processing system of claim 13 , wherein the dicing channel is used for a through silicon optical via to connect a first memory wafer of the plurality of memory wafers to a second memory wafer of the plurality of memory wafers.

16. An integrated wafer-level processing system comprising:
a memory wafer; and
a plurality of processing elements, each of the plurality of processing elements connected to the memory wafer via a data connection, wherein the data connection is disposed between the processing element and the memory wafer only near one peripheral area of the processing element, remaining peripheral areas of the processing element being free of data connections.

17. The integrated wafer-level processing system of claim 16 , wherein the memory wafer comprises a plurality of memory elements and the plurality of memory elements comprise a plurality of dynamic random access memory elements.

18. The integrated wafer-level processing system of claim 16 , wherein the memory wafer comprises a plurality of memory elements and the plurality of memory elements comprise a plurality of flash memory elements and a plurality of nonvolatile memory elements.

Assignees

• IBM

Inventors

• Emma Philip G
• Hunter Hillery C
• Knickerbocker John U

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title