High aspect ratio vertical interconnect access (via) interconnections in magnetic random access memory (MRAM) bit cells

Patent metadata

Field	Value
Publication number	US-9704919-B1
Application number	US-201615192068-A
Country	US
Kind code	B1
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

High aspect ratio vertical interconnect access (via) interconnections in magnetic random access memory (MRAM) bit cells are disclosed. In one aspect, an exemplary MRAM bit cell includes a coupling column interconnecting an access transistor and a magnetic tunnel junction (MTJ) therein. The coupling column is disposed across a plurality of interconnection layers. In one aspect, the coupling column comprises a high aspect ratio via. In another aspect, the high aspect ratio via is connected directly between a drain contact coupled to a drain of the access transistor and to an end electrode of the MTJ such that no interconnection line and/or interconnection island is provided in the coupling column. In certain aspects, the coupling column may be disposed between an interconnection line and an adjacent interconnection line without increasing an existing interconnection line pitch, thus allowing for a reduction in MRAM bit cell pitch.

First claim

What is claimed is:

1. A magnetic random access memory (MRAM) bit cell, comprising:
a substrate;
an active semiconductor layer disposed above the substrate, the active semiconductor layer comprising an access transistor, the access transistor comprising a gate, a source, and a drain;
a source contact coupled to the source of the access transistor;
a drain contact coupled to the drain of the access transistor;
a dielectric layer comprising a plurality of interconnection layers disposed above the active semiconductor layer, each interconnection layer comprising at least one interconnection line;
a source line comprising an interconnection line of a first interconnection layer of the plurality of interconnection layers, the source line coupled to the source contact; and
a magnetic tunnel junction (MTJ) coupling column disposed across at least two interconnection layers of the plurality of interconnection layers between the drain contact and an MTJ, the MTJ coupling column comprising a vertical interconnect access (via) coupling a first end electrode of the MTJ to the drain contact without coupling to any interconnection lines in the at least two interconnection layers;
the MTJ comprising a tunnel junction disposed between the first end electrode and a second end electrode; and
a bit line comprising an interconnection line of a second interconnection layer of the plurality of interconnection layers, the bit line coupled to the second end electrode of the MTJ.

2. The MRAM bit cell of claim 1 , further comprising a dielectric spacer layer disposed around the via.

3. The MRAM bit cell of claim 1 , wherein the via has a height-to-width aspect ratio of at least 10 (ten).

4. The MRAM bit cell of claim 1 , wherein the first interconnection layer of the plurality of interconnection layers comprises a plurality of interconnection lines;
wherein the via is disposed between a first interconnection line of the plurality of interconnection lines and a second interconnection line of the plurality of interconnection lines; and
wherein the second interconnection line is adjacent to the first interconnection line and separated from the first interconnection line by at least an interconnection line pitch of the plurality of interconnection lines.

5. The MRAM bit cell of claim 1 , wherein the via comprises a top end and a bottom end, the bottom end connected to the drain contact and the top end connected to the MTJ.

6. The MRAM bit cell of claim 1 , wherein:
the bit line is configured to receive a read voltage; and
the source line is configured to receive a source read voltage.

7. The MRAM bit cell of claim 1 , wherein:
the bit line is configured to receive a write voltage; and
the source line is configured to receive a source write voltage.

8. The MRAM bit cell of claim 1 , wherein the access transistor comprises an n-type metal oxide semiconductor (MOS) (NMOS) transistor.

9. The MRAM bit cell of claim 1 integrated into an integrated circuit (IC).

10. The MRAM bit cell of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a smart phone; a tablet; a phablet; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; a medical device; and an automobile.

11. A magnetic random access memory (MRAM) bit cell array, comprising:
a plurality of MRAM bit cells, each MRAM bit cell comprising:
a substrate;
an active semiconductor layer disposed above the substrate, the active semiconductor layer comprising an access transistor, the access transistor comprising a gate, a source, and a drain;
a source contact coupled to the source of the access transistor;
a drain contact coupled to the drain of the access transistor;
a dielectric layer comprising a plurality of interconnection layers disposed above the active semiconductor layer, each interconnection layer comprising at least one interconnection line;
a source line comprising an interconnection line of a first interconnection layer of the plurality of interconnection layers, the source line coupled to the source contact; and
a magnetic tunnel junction (MTJ) coupling column disposed across at least two interconnection layers of the plurality of interconnection layers between the drain contact and an MTJ, the MTJ coupling column comprising a vertical interconnect access (via) coupling a first end electrode of the MTJ to the drain contact without coupling to any interconnection lines in the at least two interconnection layers;
the MTJ comprising a tunnel junction disposed between the first end electrode and a second end electrode; and
a bit line comprising an interconnection line of a second interconnection layer of the plurality of interconnection layers, the bit line coupled to the second end electrode of the MTJ,

wherein a via of a first MRAM bit cell of the plurality of MRAM bit cells is disposed between a source line of the first MRAM bit cell of the plurality of MRAM bit cells and a source line of a second MRAM bit cell of the plurality of MRAM bit cells disposed adjacent to the first MRAM bit cell; and
wherein the source line of the first MRAM bit cell and the source line of the second MRAM bit cell are separated by an interconnection line pitch.

12. The MRAM bit cell array of claim 11 , wherein the via of the first MRAM bit cell has a height-to-width aspect ratio of at least 10 (ten).

13. The MRAM bit cell array of claim 11 , wherein the via of the first MRAM bit cell comprises a top end and a bottom end, the bottom end connected to a drain contact of the first MRAM bit cell and the top end connected to an MTJ of the first MRAM bit cell.

14. The MRAM bit cell array of claim 11 , wherein each MRAM bit cell among the plurality of MRAM bit cells further comprises a dielectric spacer layer disposed around the via.

15. The MRAM bit cell array of claim 11 , wherein, for each MRAM bit cell among the plurality of MRAM bit cells:
the first interconnection layer of the plurality of interconnection layers comprises a plurality of interconnection lines;
the via is disposed between a first interconnection line of the plurality of interconnection lines and a second interconnection line of the plurality of interconnection lines; and
the second interconnection line is adjacent to the first interconnection line and separated from the first interconnection line by at least an interconnection line pitch of the plurality of interconnection lines.

16. The MRAM bit cell array of claim 11 , wherein, for each MRAM bit cell among the plurality of MRAM bit cells:
the bit line is configured to receive a read voltage; and
the source line is configured to receive a source read voltage.

17. The MRAM bit cell array of claim 11 , wherein, for each MRAM bit cell among the plurality of MRAM bit cells:
the bit line is configured to receive a write voltage; and
the source line is configured to receive a source write voltage.

18. The MRAM bit cell array of claim 11 , wherein the access transistor in each MRAM bit cell among the plurality of MRAM bit cells comprises an n-type metal oxide semiconductor (MOS) (NMOS) transistor.

19. The

Assignees

• Qualcomm Inc

Inventors

• Lu Yu
• Chen Wei-Chuan
• Kan Jimmy Jianan
• Kang Seung Hyuk

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/46

  using a liquid · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title