Nonvolatile SRAM

Patent metadata

Field	Value
Publication number	US-10748602-B2
Application number	US-201616079400-A
Country	US
Kind code	B2
Filing date	Mar 23, 2016
Priority date	Mar 23, 2016
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.

First claim

What is claimed is:

1. An apparatus comprising:
a volatile static memory cell that includes:
cross coupled inverters;
a first access transistor having a source coupled to the cross coupled inverter; and
a second access transistor having a drain coupled to the cross coupled inverter; and

a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell, the pair of nonvolatile RRAM memory cells comprising a first RRAM memory cell and a second RRAM memory cell,
the first RRAM memory cell comprising:
a first resistive memory element coupled to a first bit line, and
a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell;
the first selector transistor including:
a drain communicatively coupled to the source of the first access transistor; and
a gate communicatively coupled to a selector word line, the selector word line to cause a transfer of logic state from the first output node of the volatile SRAM memory cell to the first RRAM memory cell prior to entry into a low power state; and

the second RRAM memory cell comprising:
a second resistive memory element coupled to a second bit line, and
a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell;
the second selector transistor including:
a drain communicatively coupled to the drain of the second access transistor; and

a gate communicatively coupled to the selector word line, the selector word line to cause a transfer of logic state from the second output node of the volatile SRAM memory cell to the second RRAM memory cell prior to entry into the low power state.

2. The apparatus of claim 1 , wherein the first resistive memory element comprises a first positive electrode and a first negative electrode and the second resistive memory element comprises a second positive electrode and a second negative electrode.

3. The apparatus of claim 2 , wherein the first positive electrode is coupled to the first bit line and the second positive electrode is coupled to the second bit line.

4. The apparatus of claim 2 , wherein the first positive electrode is coupled to the first selector transistor and the second positive electrode is coupled to the second selector transistor.

5. The apparatus of claim 1 , wherein the first RRAM memory cell and the second RRAM memory cell are formed using an advanced CMOS (complementary metal oxide semiconductor) process.

6. The apparatus of claim 5 , wherein a minimum feature size is less than or equal to 20 nanometers (nm).

7. A system comprising:
a processor comprising at least one core;
a memory controller; and
a memory array comprising a plurality of nonvolatile static random access memory (SRAM) memory cells, each nonvolatile SRAM memory cell comprising:
a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile SRAM memory cell, the pair of nonvolatile RRAM memory cells comprising a first RRAM memory cell and a second RRAM memory cell,
the first RRAM memory cell comprising:
a first resistive memory element coupled to a first bit line, and
a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell;
the first selector transistor including a gate communicatively coupled to a selector word line, the selector word line to cause a transfer of logic state from the first output node of the volatile SRAM memory cell to the first RRAM memory cell prior to entry into a low power state; and

the second RRAM memory cell comprising:
a second resistive memory element coupled to a second bit line, and
a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell;
the second selector transistor including a gate communicatively coupled to the selector word line, the selector word line to cause a transfer of logic state from the second output node of the volatile SRAM memory cell to the second RRAM memory cell prior to entry into the low power sta.

8. The system of claim 7 , wherein each resistive memory element occupies a plurality of adjacent back end layers of a monolithic integrated circuit.

9. The system of claim 7 , wherein the first resistive memory element comprises a first positive electrode and a first negative electrode and the second resistive memory element comprises a second positive electrode and a second negative electrode.

10. The system of claim 9 , wherein the first positive electrode is coupled to the first bit line and the second positive electrode is coupled to the second bit line.

11. The system of claim 9 , wherein the first positive electrode is coupled to the first selector transistor and the second positive electrode is coupled to the second selector transistor.

12. The system of claim 7 , wherein the first RRAM memory cell and the second RRAM memory cell are formed using an advanced CMOS (complementary metal oxide semiconductor) process.

13. The system of claim 12 , wherein a minimum feature size is less than or equal to 20 nanometers (nm).

14. The system of claim 7 , further comprising power management logic.

15. The system of claim 14 , wherein the power management logic is to store data contained in the volatile SRAM memory cell to the pair of nonvolatile RRAM memory cells and to transition the volatile SRAM memory cell to the low power state.

16. The system of claim 15 , wherein the power management logic is further to transition the volatile SRAM memory cell out of the low power state and to restore the data to the volatile SRAM memory cell.

Assignees

• Intel Corp

Inventors

• Liu Huichu
• Manipatruni Sasikanth
• Morris Daniel H
• Vaidyanathan Kaushik
• Mukherjee Niloy
• Nikonov Dmitri E
• Young Ian
• Karnik Tanay

Classifications

• G11C2213/71

  Three dimensional array · CPC title

• G11C14/009

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C11/413 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title