RRAM array with current limiting element

Patent metadata

Field	Value
Publication number	US-10163505-B2
Application number	US-201715836028-A
Country	US
Kind code	B2
Filing date	Dec 8, 2017
Priority date	Nov 16, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A resistive random access memory (RRAM) circuit is provided. In some embodiments, the RRAM circuit has a plurality of RRAM cells. A bit-line decoder is configured to concurrently apply a forming signal to the plurality of RRAM cells. A current limiting element is configured to concurrently limit a current of the forming signal applied to the plurality of RRAM cells.

First claim

What is claimed is:

1. A resistive random access memory (RRAM) circuit, comprising:
a plurality of RRAM cells;
a plurality of bit-lines coupled to the plurality of RRAM cells;
a bit-line decoder configured to concurrently apply a forming signal to the plurality of RRAM cells, wherein the bit-line decoder is configured to apply a write voltage to the plurality of bit-lines that is smaller than a voltage used to apply the forming signal; and
a current limiting element configured to concurrently limit a current of the forming signal applied to the plurality of RRAM cells, which is concurrently applied to the plurality of bit-lines.

2. The RRAM circuit of claim 1 , wherein the current limiting element is configured to limit the current of the forming signal to a value that is smaller than a current value used to perform a write operation on one of the plurality of RRAM cells.

3. The RRAM circuit of claim 1 , wherein the forming signal is configured to form initial conductive filaments within the plurality of RRAM cells.

4. The RRAM circuit of claim 1 , further comprising:
a word-line operatively coupled to the plurality of RRAM cells by way of separate access transistors.

5. The RRAM circuit of claim 1 , further comprising:
a plurality of source-lines coupled to the plurality of RRAM cells, wherein the current limiting element is coupled to the plurality of RRAM cells by the plurality of source-lines.

6. The RRAM circuit of claim 1 , wherein the current limiting element comprises a plurality of discrete current limiting components, which are respectively coupled to one of the plurality of RRAM cells.

7. The RRAM circuit of claim 1 , wherein the current limiting element comprises:
a plurality of transistor devices, wherein respective ones of the plurality of transistor devices are coupled to one of the plurality of RRAM cells; and
a current source coupled to gate terminals of the plurality of transistor devices.

8. The RRAM circuit of claim 1 , further comprising:
a control unit configured to concurrently operate the current limiting element to limit the current applied to the plurality of RRAM cells and to operate the bit-line decoder to apply the forming signal to the plurality of RRAM cells.

9. The RRAM circuit of claim 8 , wherein the control unit is further configured to decouple the current limiting element from the plurality of RRAM cells or to turn off the current limiting element during performance of a read operation and a write operation on one of the plurality of RRAM cells.

10. A resistive random access memory (RRAM) circuit, comprising:
a plurality of RRAM devices;
a bit-line decoder coupled to a plurality of bit-lines coupled to the plurality of RRAM devices, wherein the bit-line decoder is configured to concurrently apply a forming signal to the plurality of RRAM devices and the plurality of bit-lines, wherein the bit-line decoder is configured to apply a write voltage to the plurality of bit-lines that is smaller than a voltage used to apply the forming signal; and
a current limiting element configured to concurrently limit a current of the forming signal on the plurality of bit-lines and the plurality of RRAM devices.

11. The RRAM circuit of claim 10 , further comprising:
a plurality of access transistors respectively having a source terminal coupled to one of the plurality of RRAM devices; and
a word-line coupled to gate terminals of the plurality of access transistors.

12. The RRAM circuit of claim 10 , wherein the current limiting element comprises:
a plurality of transistor devices, wherein respective ones of the plurality of transistor devices are coupled to one of the plurality of RRAM devices; and
a diode connected transistor having a source terminal coupled to a current source and a gate terminal coupled to the source terminal and to gate terminals of the plurality of transistor devices.

13. The RRAM circuit of claim 10 , further comprising:
a plurality of source-lines coupled to the plurality of RRAM devices, wherein a first electrode of a first one of the plurality of RRAM devices is coupled to a first one of the plurality of bit-lines and a second electrode of the first one of the plurality of RRAM devices is coupled to a first one of the plurality of source-lines; and
wherein the current limiting element is coupled to the plurality of RRAM devices by the plurality of source-lines.

14. The RRAM circuit of claim 10 , wherein the current limiting element is configured to limit the current of the forming signal applied to the plurality of bit-lines to a value that is smaller than a current value used to perform a write operation on one of the plurality of RRAM devices.

15. A method of operating an RRAM circuit, comprising:
activating a word-line coupled to a row of RRAM cells within an RRAM array;
concurrently applying a forming signal to a plurality of bit-lines coupled to a plurality of RRAM cells within the row of RRAM cells, wherein a forming voltage used to apply the forming signal is greater than a write voltage used to perform a write operation on the plurality of bit-lines; and
concurrently limiting a current of the forming signal applied to the plurality of bit-lines, which is concurrently applied to the plurality of RRAM cells.

16. The method of claim 15 , wherein the forming signal forms an initial conductive filaments within the plurality of RRAM cells.

17. The method of claim 15 , further comprising:
decoupling the current limiting element from the plurality of RRAM cells or turning off the current limiting element during performance of a read operation and the write operation on one of the plurality of RRAM cells.

18. The method of claim 15 , wherein the current limiting element is configured to limit the current of the forming signal to a value that is smaller than a current value used to perform the write operation on the plurality of RRAM cells.

19. The method of claim 15 , further comprising:
simultaneously applying a second voltage smaller than the forming voltage to a plurality of source-lines, wherein the plurality of bit-lines are coupled to first electrodes of the plurality of RRAM cells, and wherein the plurality of source-lines are coupled to second electrodes of the plurality of RRAM cells.

20. The RRAM circuit of claim 10 , further comprising:
one or more additional current limiting elements configured to independently limit a current on one of the plurality of bit-lines during a write operation.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Chia-Fu
• Chih Yu-Der
• Lin Hon-Jarn

Classifications

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C2013/0083

  Write to perform initialising, forming process, electro forming or conditioning · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C2013/0088

  Write with the simultaneous writing of a plurality of cells · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title