Solid-state imaging device, manufacturing method thereof, and electronic apparatus
US-9478572-B2 · Oct 25, 2016 · US
US10741399B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10741399-B2 |
| Application number | US-201815896940-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 14, 2018 |
| Priority date | Sep 24, 2004 |
| Publication date | Aug 11, 2020 |
| Grant date | Aug 11, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.
Opening claim text (preview).
What is claimed is: 1. A substrate, comprising: a semiconductor substrate, wherein a surface layer of the semiconductor substrate exhibits a modified topography having a plurality of irregular features having an average height less than about 1 micrometer and an average width in a range of about 100 nm to about 500 nm, each of said irregular features exhibiting an undulating side surface extending from a base to a tip, wherein said plurality of irregular features exhibit an average separation between adjacent features of about 500 nm. 2. The substrate of claim 1 , wherein said irregular features have an average width in a range of about 100 nm to about 300 nm. 3. The substrate of claim 1 , wherein said plurality of irregular features exhibit an average ratio of height to width in a range from 3 to 10. 4. The substrate of claim 1 , wherein said semiconductor substrate comprises a silicon substrate. 5. The substrate of claim 1 , wherein said semiconductor substrate comprises an n-doped silicon substrate. 6. The substrate of claim 1 , wherein said surface layer has a thickness in a range of about 20 nm to about 1 micrometer. 7. The substrate of claim 1 , wherein said irregular features have an average height in a range of about 500 nm to less than about 1 micrometer. 8. The substrate of claim 1 , wherein said features protrude above an original surface of the semiconductor substrate by a distance in a range of about 100 nm to about 300 nm. 9. The substrate of claim 1 , wherein at least a portion of said plurality of irregular features extend from a base to a tip at a level above an original surface of the semiconductor substrate by a distance in a range of about 100 nm to about 300 nm. 10. A substrate, comprising: a semiconductor substrate, wherein a surface layer of the semiconductor substrate includes a plurality of protrusions of various heights, the plurality of protrusions characterized by an average width in a range of about 100 nm to about 300 nm and average ratio of height to width in a range of 3 to 10, wherein said protrusions exhibit an average separation between adjacent protrusions of about 500 nm. 11. The substrate of claim 10 , wherein said protrusions exhibit height variations characterized by an average height in a range of about 500 nm to about 1 micrometer. 12. The substrate of claim 10 , wherein said protrusions protrude above an original surface of the semiconductor substrate by a distance in a range of about 100 nm to about 300 nm. 13. The substrate of claim 10 , wherein said semiconductor substrate comprises a silicon substrate. 14. The substrate of claim 10 , wherein said semiconductor substrate comprises an n-doped silicon substrate. 15. The substrate of claim 10 , wherein said protrusions are disposed with a surface layer of the substrate having a thickness in a range of about 20 nm to about 1 micrometer. 16. A substrate, comprising: a semiconductor substrate, wherein a surface layer of the semiconductor substrate includes a plurality of protrusions of various heights, each of the plurality of protrusions characterized by an undulating side surface extending from a base to a tip, said plurality of protrusions having an average height less than about 1 micrometer, wherein said protrusions have a width in a range of about 100 nm to about 500 nm. 17. The substrate of claim 16 , wherein said plurality of protrusions exhibit an average ratio of height to width in a range of 3 to 10. 18. The substrate of claim 16 , wherein said plurality of protrusions exhibit an average separation between adjacent protrusions of about 500 nm.
for wet etching · CPC title
Etching of wafers, substrates or parts of devices · CPC title
using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase · CPC title
being group IV material · CPC title
Pulsed laser beam · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.