ReRAM structure formed by a single process

US10734575B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10734575-B2
Application numberUS-201916566349-A
CountryUS
Kind codeB2
Filing dateSep 10, 2019
Priority dateMay 1, 2018
Publication dateAug 4, 2020
Grant dateAug 4, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a resistive random access memory device, the method comprising: forming, in a reactor chamber and under vacuum, a bottom electrode layer composed of a metal selected from tungsten (W) and molybdenum (Mo) on a surface of a substrate by first sputtering the metal from a target in a first sputtering atmosphere composed entirely of an inert gas; forming, without breaking the vacuum, a resistive switching element composed of an oxide of the metal on a surface of the bottom electrode layer by second sputtering the metal from the target in a second sputtering atmosphere composed of the inert gas and oxygen; and forming, without breaking the vacuum, a first top electrode layer composed of a nitride of the metal on a surface of the resistive switching element by third sputtering the metal from the target in a third sputtering atmosphere composed of the inert gas and nitrogen. 2. The method of claim 1 , further comprising forming, without breaking the vacuum, a second top electrode layer composed of the metal on a surface of the first top electrode layer by fourth sputtering the metal from the target in a same sputtering atmosphere as the first sputtering atmosphere. 3. The method of claim 2 , wherein the metal that provides each of the bottom electrode layer, the resistive switching element, the first top electrode layer, and the second top electrode layer is tungsten (W). 4. The method of claim 3 , wherein the bottom electrode is composed of W, the resistive switching element is composed of WO 3 , and the first top electrode layer is composed of WN x , wherein 0.5<x<2. 5. The method of claim 2 , wherein the metal that provides each of the bottom electrode layer, the resistive switching element, the first top electrode layer, and the second top electrode layer is molybdenum (Mo). 6. The method of claim 5 , wherein the bottom electrode layer is composed of Mo, the resistive switching element is composed of MoO y , wherein 2<y<3 and the first top electrode layer is composed of a nitride of Mo. 7. The method of claim 1 , wherein the inert gas is argon. 8. The method of claim 1 , wherein the substrate is composed of a semiconductor material having semiconducting properties. 9. The method of claim 1 , wherein the substrate is composed of glass or a dielectric material. 10. The method of claim 1 , wherein an interface between the bottom electrode layer and the resistive switching element and an interface between the first top electrode layer and the resistive switching element having no intermixing of materials from either side of both interfaces. 11. The method of claim 1 , wherein the first sputtering is performed at a temperature between 20° C. to 375° C. 12. The method of claim 11 , wherein the first sputtering is performed using a process pressure between 2 mTorr and 60 mTorr. 13. The method of claim 1 , wherein the second sputtering is performed at a temperature between 100° C. and 300° C. 14. The method of claim 1 , wherein the third sputtering is performed at a temperature between 20° C. to 375° C. 15. The method of claim 1 , wherein the amount of oxygen used in the second sputtering is from 1 percent to 80 percent of oxygen within the second sputtering atmosphere. 16. The method of claim 1 , wherein the amount of nitrogen used in the third sputtering is from 1 percent to 70 percent of nitrogen within the third sputtering atmosphere. 17. The method of claim 2 , wherein the fourth sputtering is performed at a temperature between 20° C. to 375° C. 18. The method of claim 1 , wherein the bottom electrode layer has outermost sidewalls that are vertically aligned to outermost sidewalls of both the resistive switching element and the first top electrode layer. 19. The method of claim 1 , wherein the resistive switching element is composed of a single material selected from the group consisting of WO 2 , W 2 O 5 , or WO 3 . 20. The method of claim 1 , wherein the resistive switching element is composed of MoO y wherein 2<y<3.

Assignees

Inventors

Classifications

  • adapted for supplying ionic species · CPC title

  • Formation of switching materials, e.g. deposition of layers · CPC title

  • adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

  • H10N70/24Primary

    based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

  • by physical vapor deposition, e.g. sputtering · CPC title

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What does patent US10734575B2 cover?
A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive rando…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10N70/24. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 04 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).