Monolithic integration techniques for fabricating photodetectors with transistors on same substrate

Patent metadata

Field	Value
Publication number	US-10734533-B2
Application number	US-201715472177-A
Country	US
Kind code	B2
Filing date	Mar 28, 2017
Priority date	Nov 24, 2014
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

First claim

What is claimed is:

1. A device comprising:
a semiconductor substrate;
a semiconductor transistor formed on said semiconductor substrate; and
a semiconductor photodetector formed on said semiconductor substrate,
wherein a top surface of a light absorption material of the semiconductor photodetector is higher than a bottom surface of a lowest layer of metal interconnects for the semiconductor transistor,
wherein a metal interconnect is a substantially horizontal wire between devices, and
wherein horizontal is parallel to the semiconductor substrate.

2. The device of claim 1 , further comprising:
a passivation spacer on said light absorption material.

3. The device of claim 1 , further comprising a passivation spacer on a sidewall of the semiconductor photodetector.

4. The device of claim 1 , further comprising:
contact plugs for the transistor, wherein the contact plugs for the transistor are made of refractory materials formed during a middle-of-line (MOL) fabrication stage; and
contact plugs for the photodetector, wherein the contact plugs for the photodetector are entirely made of non-refractory materials from metal interconnect layers formed during a back-end-of-line (BEOL) fabrication stage, without any of the refractory materials from said MOL fabrication stage.

5. The device of claim 1 , wherein the photodetector includes a P-I-N structure having a highly-doped p-type semiconductor region, a highly-doped n-type semiconductor region, and an intrinsic photosensitive semiconductor region located between said p-type and n-type semiconductor regions,
wherein the intrinsic photosensitive semiconductor region comprises a stack of semiconductor materials including substrate semiconductor material with a first dielectric constant and a photosensitive material with a second dielectric constant, the second dielectric constant higher than the first dielectric constant.

6. The device of claim 5 , wherein a thickness ratio between the substrate semiconductor material and other semiconductor materials in the intrinsic photosensitive semiconductor region combined is greater than 1 to 5.

7. The device of claim 1 , further comprising:
a select number of dummy fill shapes about a size of the transistor, wherein the dummy fill shapes about the size of the transistor are formed at a same height as the transistor; and
a select number of dummy fill shapes about a size of the photodetector, wherein the dummy fill shapes about the size of the photodetector are formed at the same height as the photodetector.

8. A device comprising:
a semiconductor substrate;
a semiconductor transistor formed on said semiconductor substrate; and
a semiconductor photodetector formed on said semiconductor substrate,
wherein the semiconductor photodetector includes a light absorption region with at least two light absorption layers, at least one of them being a seed layer, and
wherein vertical sidewalls of the at least two light absorption layers are misaligned.

9. The device of claim 8 , wherein at least one set of metal contact plugs for the transistor or the photodetector is formed between the two or more separate material forming processes.

10. The device of claim 9 , wherein at least one of the two or more separate forming processes is performed during or after a middle-of-line (MOL) fabrication stage.

11. The device of claim 8 , wherein said at least two light absorption layers are of a substantially same light absorption material.

12. The device of claim 11 , wherein said substantially same material includes germanium.

13. The device of claim 8 , further comprising:
a passivation spacer on said absorption region, wherein the passivation spacer material includes amorphous-Si, poly-crystalline Si, nitride, high-k dielectric, silicon dioxide (SiO 2 ), or any combination thereof.

14. The device of claim 8 , further comprising:
contact plugs for the transistor, wherein the contact plugs for the transistor are made of refractory materials; and
contact plugs for the photodetector, wherein the contact plugs for the photodetector are entirely made of non-refractory materials.

15. The device of claim 8 , wherein the photodetector includes a P-I-N structure having a highly-doped p-type semiconductor region, a highly-doped n-type semiconductor region, and an intrinsic photosensitive semiconductor region located between said p-type and n-type semiconductor regions.

16. The device of claim 15 , wherein the intrinsic photosensitive semiconductor region comprises a stack of semiconductor materials including substrate semiconductor material with a first dielectric constant and a photosensitive material with a second dielectric constant, the second dielectric constant higher than the first dielectric constant.

17. The device of claim 15 , wherein a thickness ratio between the substrate semiconductor material and other semiconductor materials in the intrinsic photosensitive semiconductor region combined is greater than 1 to 5.

18. The device of claim 8 , further comprising:
a select number of dummy fill shapes about a size of the transistor, wherein the dummy fill shapes about the size of the transistor are formed at a same height as the transistor; and
a select number of dummy fill shapes about a size of the photodetector, wherein the dummy fill shapes about the size of the photodetector are formed at the same height as the photodetector.

Assignees

• Artilux Inc

Inventors

• Cheng Szu-Lin
• Chen Shu-Lu

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10F71/129

  Passivating · CPC title