Monolithic integration techniques for fabricating photodetectors with transistors on same substrate

Patent metadata

Field	Value
Publication number	US-9640421-B2
Application number	US-201514950902-A
Country	US
Kind code	B2
Filing date	Nov 24, 2015
Priority date	Nov 24, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

First claim

What is claimed is:

1. A method for fabricating a photodetector and a transistor on a same semiconductor substrate, the method comprising:
(1) on a semiconductor substrate, epitaxially growing a first layer of light absorption material of the photodetector over an area where the photodetector is to be formed;
(2) after said growing the first layer of light absorption material, forming at least one layer of metallic contact plugs for the transistor; and
(3) after said forming at least one layer of metallic contact plugs, forming a second layer of light absorption material of the photodetector, wherein the second layer of light absorption material is formed atop the first layer of the light absorption material, such that the two layers of light absorption material, having a substantially same material, form a single light absorption region for the photodetector,
wherein the first layer and second layers of light absorption material are formed by using separate lithography processes, and wherein the separate lithography processes leave a sidewall misalignment on a structure that constitutes the single light absorption region.

2. The method of claim 1 , wherein said epitaxially growing the first layer of light absorption material is performed at a temperature suitable for the photodetector's light absorption material to epitaxially grow on a heterogeneous surface.

3. The method of claim 1 , wherein said forming the second layer of light absorption material is performed at a temperature suitable for the photodetector's light absorption material to epitaxially grow on a homogeneous surface.

4. The method of claim 1 , wherein said forming the second layer of light absorption material is performed at a temperature lower than said epitaxially growing the first layer of light absorption material.

5. The method of claim 1 , wherein said forming the second layer of light absorption material is performed at a temperature lower than a tolerance temperature of the formed metallic contact plugs for the transistor.

6. The method of claim 1 , wherein said epitaxially growing the first layer of light absorption material is performed at a temperature higher than a tolerance temperature of the formed metallic contact plugs for the transistor.

7. The method of claim 1 , wherein said epitaxially growing the first layer of light absorption material comprises:
performing a surface cleaning process at a temperature higher than a tolerance temperature of the formed metallic contact plugs for the transistor.

8. The method of claim 1 , wherein a top surface of the second layer of light absorption material is higher than a bottom surface of a lowest layer of metal interconnects for the transistor.

9. The method of claim 1 , wherein said forming the second layer of light absorption material comprises:
removing materials deposited over the photodetector from preceding processes to expose the first layer of light absorption material.

10. The method of claim 9 , wherein said forming the second layer of light absorption material further comprises:
epitaxially growing the second layer of light absorption material atop the first layer of light absorption material at least until a height of the single light absorption region is higher than the at least one layer of metallic contact plugs for the transistor.

11. The method of claim 1 , further comprising:
before said forming the second layer of light absorption material with an opening, forming a passivation spacer on a sidewall of the opening to passivate said second layer of light absorption material to reduce device dark-current.

12. The method of claim 1 , further comprising:
growing, on the first or second layer of light absorption material, a passivation layer having substrate material; and
directionally etching said passivation layer to form a passivation spacer on said first or second layer of light absorption material.

13. A semiconductor manufacturing system having machinery configured to perform a method for fabricating a photodetector and a transistor on a same semiconductor substrate, the method comprising:
(1) on a semiconductor substrate, epitaxially growing a first layer of light absorption material of the photodetector over an area where the photodetector is to be formed;
(2) after said growing the first layer of light absorption material, forming at least one layer of metallic contact plugs for the transistor; and
(3) after said forming at least one layer of metallic contact plugs, forming a second layer of light absorption material of the photodetector, wherein the second layer of light absorption material is formed atop the first layer of the light absorption material, such that the two layers of light absorption material, having a substantially same material, form a single light absorption region for the photodetector,
wherein the first layer and second layers of light absorption material are formed by using separate lithography processes, and wherein the separate lithography processes leave a sidewall misalignment on a structure that constitutes the single light absorption region.

14. The manufacturing system of claim 13 , wherein said epitaxially growing the first layer of light absorption material is performed at a temperature suitable for the photodetector's light absorption material to epitaxially grow on a heterogeneous surface.

15. The manufacturing system of claim 13 , wherein said forming the second layer of light absorption material is performed at a temperature suitable for the photodetector's light absorption material to epitaxially grow on a homogeneous surface.

16. The manufacturing system of claim 13 , wherein said forming the second layer of light absorption material is performed at a temperature lower than said epitaxially growing the first layer of light absorption material.

17. The manufacturing system of claim 13 , wherein said forming the second layer of light absorption material is performed at a temperature lower than a tolerance temperature of the formed metallic contact plugs for the transistor.

18. The manufacturing system of claim 13 , wherein said epitaxially growing the first layer of light absorption material is performed at a temperature higher than a tolerance temperature of the formed metallic contact plugs for the transistor.

19. The manufacturing system of claim 13 , wherein said epitaxially growing the first layer of light absorption material comprises:
performing a surface cleaning process at a temperature higher than a tolerance temperature of the formed metallic contact plugs for the transistor.

20. The manufacturing system of claim 13 , wherein a top surface of the second layer of light absorption material is higher than a bottom surface of a lowest layer of metal interconnects for the transistor.

21. The manufacturing system of claim 13 , wherein said forming the second layer of light absorption material comprises:
removing materials deposited over the photodetector from preceding processes to expose the first layer of light absorption material.

22. The manufacturing system of claim 21 , wherein said forming the second layer of light absorption material further comprises:
epitaxially growing the second layer of light absorption material atop the first layer of light absorption material at least until a height of the single light absorption region is higher than the at least one layer of metallic contact plugs for the transistor.

23. The manufacturing system of claim

Assignees

• Artilux Inc
• Artilux Inc

Inventors

• Cheng Szu-Lin
• Chen Shu-Lu

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10F71/129

  Passivating · CPC title