Monolithic integration techniques for fabricating photodetectors with transistors on same substrate

Patent metadata

Field	Value
Publication number	US-9524898-B2
Application number	US-201514950494-A
Country	US
Kind code	B2
Filing date	Nov 24, 2015
Priority date	Nov 24, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

First claim

What is claimed is:

1. A method for fabricating a photodetector and a transistor on a same semiconductor substrate, the method comprising:
(1) during a front-end-of-line (FEOL) fabrication stage, forming the transistor on a semiconductor substrate;
(2) during a middle-of-line (MOL) fabrication stage and before the photodetector is formed on the semiconductor substrate, forming contact plugs for the transistor by using refractory materials;
(3) forming the photodetector on the semiconductor substrate; and
(4) only during an back-end-of-line (BEOL) fabrication stage, forming contact plugs for the photodetector.

2. The method of claim 1 , wherein said contact plugs for the photodetector are formed by using non-refractory materials.

3. The method of claim 1 , further comprising:
during said BEOL fabrication stage, forming additional contact plugs on said contact plugs for the transistor, wherein the additional contact plugs for the transistor are to (a) be electrically connected to said formed contact plugs for the transistor and (b) reach a same height as the contact plugs for the photodetector.

4. The method of claim 3 , wherein a portion of the additional contact plugs is configured as interconnects that provide inter-device signal transfer for the transistor.

5. The method of claim 1 , wherein said forming contact plugs for the photodetector comprises:
in a first step during the BEOL fabrication stage, forming a first set of contact plugs for the photodetector by using a first metal material; and
in a subsequent step during the BEOL fabrication stage, forming a second set of contact plugs for the photodetector by using a second metal material,
wherein the first and second sets of contact plugs are for different doped regions of the photodetector.

6. The method of claim 1 , further comprising:
before said forming the transistor, forming a structure having a mesa for the transistor and a mesa for the photodetector; and
adjusting a relative height between the mesa for the photodetector and the mesa for the transistor until a top surface of the mesa for the photodetector is lower than a top surface of the mesa for the transistor.

7. The method of claim 1 , wherein said contact plugs for the transistor are the first metal directly contacting the formed transistor, and wherein said contact plugs for the transistor are formed in arrays of pillars or bars.

8. The method of claim 1 , wherein said MOL stage further comprises:
depositing a dielectric layer that is the first dielectric layer covering the transistor.

9. The method of claim 1 , wherein said contact plugs for the transistor are formed to be entirely below a bottom surface of a first interconnect layer for the transistor and are positioned to be electrically coupled with at least one of: the transistor's gate area, the transistor's source area, or the transistor's drain area.

10. The method of claim 9 , wherein a first group of said contact plugs for the photodetector are formed to be entirely below a bottom surface of a first interconnect layer for the photodetector and are positioned to be electrically coupled with a first doped region of the photodetector.

11. The method of claim 10 , wherein a second group of said contact plugs for the photodetector are formed to be at least partially above the bottom surface of the first interconnect layer for the transistor and are positioned to be electrically coupled with a second doped region of the photodetector, the second doped region having a different polarity than the first doped region.

12. The method of claim 1 , wherein said BEOL stage further comprises: sequentially forming a number of interconnect layers above layers formed during the MOL stage.

13. The method of claim 1 , wherein said forming contact plugs for the photodetector comprises:
forming contact plugs for the photodetector's P and N regions by using different BEOL metals during the BEOL stage.

14. The method of claim 1 , wherein materials used to form said contact plugs for the transistor comprise at least one of: tungsten, titanium, or titanium nitride.

15. The method of claim 1 , wherein materials used to form said contact plugs for the photodetector comprise interconnect metals including at least one of: copper or aluminum.

Assignees

• Artilux Inc

Inventors

• Cheng Szu-Lin
• Chen Shu-Lu

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10F71/129

  Passivating · CPC title