Etching method and substrate processing system

US10734243B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10734243-B2
Application numberUS-201715841147-A
CountryUS
Kind codeB2
Filing dateDec 13, 2017
Priority dateDec 13, 2016
Publication dateAug 4, 2020
Grant dateAug 4, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In an etching method for removing a processing target layer formed on a substrate for manufacturing electronic devices, a first break-through process of removing an oxide film formed on a surface of the processing target layer is performed, and a first main etching process of etching the processing target layer is performed after the first break-through process. Then, a second break-through process of removing the oxide film exposed after the first main etching process is performed, and a second main etching process of etching the processing target layer is performed after the second break-through process.

First claim

Opening claim text (preview).

What is claimed is: 1. An etching method for removing a processing target layer formed on a substrate for manufacturing electronic devices, the method comprising: a first break-through process of removing an oxide film formed on a surface of the processing target layer; a first main etching process of etching the processing target layer after the first break-through process; a second break-through process of removing an oxide film in a gap between grains of the processing target layer prior to the first main etching process, the oxide film exposed by the first main etching process; and a second main etching process of etching the processing target layer after the second break-through process, wherein an etching amount of the processing target layer in the first main etching process is smaller than an etching amount of the processing target layer in the second main etching process, and only a vicinity of a surface of the processing target layer is etched during the first main etching process. 2. The etching method of claim 1 , wherein in the first main etching process, an etching amount of the processing target layer is set to be 2000 A or above. 3. The etching method of claim 1 , further comprising: a third break-through process of removing another oxide film in a gap between grains of the processing target layer prior to the second main etching process, exposed by the second main etching process; and a third main etching process of etching the processing target layer after the third break-through process. 4. The etching method of claim 1 , wherein in the first break-through process and the second break-through process, HF gas and NH 3 gas are used as processing gases, and wherein in the first main etching process and the second main etching process, at least F 2 gas is used as a processing gas. 5. The etching method of claim 1 , wherein the processing target layer is one of a silicon layer, a silicon nitride layer and a metal layer. 6. The etching method of claim 1 , wherein the first break-through process and the second break-through process are performed without using a plasma.

Assignees

Inventors

Classifications

  • characterised by movements or sequence of movements of transfer devices · CPC title

  • Mechanical parts of transfer devices · CPC title

  • characterised by the construction of the transfer chamber · CPC title

  • in-line arrangement · CPC title

  • for drying etching · CPC title

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What does patent US10734243B2 cover?
In an etching method for removing a processing target layer formed on a substrate for manufacturing electronic devices, a first break-through process of removing an oxide film formed on a surface of the processing target layer is performed, and a first main etching process of etching the processing target layer is performed after the first break-through process. Then, a second break-through pro…
Who is the assignee on this patent?
Tokyo Electron Ltd
What technology area does this patent fall under?
Primary CPC classification H10P50/268. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 04 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).