Integrated circuit processor and method of operating the integrated circuit processor in different modes of differing thread counts

Patent metadata

Field	Value
Publication number	US-10732976-B2
Application number	US-201314655122-A
Country	US
Kind code	B2
Filing date	Jan 10, 2013
Priority date	Jan 10, 2013
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode.

First claim

The invention claimed is:

1. A integrated circuit processor comprising an instruction pipeline operable alternatively in a multi-thread mode and in a single-thread mode; wherein said instruction pipeline, when in said multi-thread mode, is arranged to process multiple threads, and when in said single-thread mode is arranged to process a single thread;
said instruction pipeline comprising multiple register sets including a first register set and a second register set, each of said multiple register sets reserved for one thread among said multiple threads when said pipeline is in said multi-thread mode, and each of said multiple register sets is capable of being used for a corresponding context layer when said instruction pipeline is in said single-thread mode, wherein, in said single-thread mode, said multiple register sets enable a context switch from a first context layer in the first register set executed during a first particular time range of the execution of the single thread to a second context layer in the second register set executed during a second particular time range of the execution of the single thread, in which the first register set stores data associated with the first context layer which includes state information for restoring an interrupted process,
wherein the integrated circuit processor further comprises a control register which is accessed in single-thread mode and has a first binary variable which indicates that the single thread may use a register set of the multiple register sets corresponding to a disabled thread of the multiple threads for the second context layer upon the context switch, and a second binary variable which identifies the second register set to be used for the second context layer upon the context switch in the single thread wherein the second binary variable of the control register identifies the second register set during execution of the first context layer, prior to the context switch to the second context layer.

2. The integrated circuit processor of claim 1 , each of said multiple register sets comprising a set of registers.

3. The integrated circuit processor of claim 1 , wherein when said pipeline is in said single-thread mode, each of said multiple register sets stores data associated with the corresponding context layer of the multiple context layers.

4. The integrated circuit processor of claim 3 , wherein said data associated with the corresponding context layer of the multiple context layers includes state information for restoring an interrupted process.

5. The integrated circuit of claim 1 , further comprising a mode selection unit for selecting an active mode among said multi-thread mode and said single-thread mode.

6. The integrated circuit processor of claim 1 , wherein said instruction pipeline is implemented in a single core of said integrated circuit processor.

7. The integrated circuit processor of claim 1 , wherein said instruction pipeline is capable of containing instructions from different threads when in said multi-thread mode.

8. The integrated circuit processor of claim 1 , wherein said instruction pipeline is arranged to contain instructions from only one thread when in said single-thread mode.

9. The integrated circuit processor of claim 1 , wherein said instruction pipeline is arranged to be flushed in response to a context change.

10. The integrated circuit processor of claim 1 , wherein said instruction pipeline is arranged to process multiple threads in an interleaved or simultaneous manner when in said multi-thread mode.

11. A method of operating an integrated circuit processor comprising an instruction pipeline, said method comprising:
operating said instruction pipeline alternatively in a multi-thread mode and in a single-thread mode;
when said instruction pipeline, is operating in said multi-thread mode, processing multiple threads in an interleaved or simultaneous manner;
when said instruction pipeline is operating in said single-thread mode, processing a single thread having multiple context layers,
wherein said instruction pipeline comprises multiple register sets including a first register set and a second register set, wherein each of said multiple register sets is reserved for one thread among said multiple threads when said pipeline is in said multi-thread mode, and each of said multiple register sets is capable of being used for a different context layer among said multiple context layers when said instruction pipeline is in said single-thread mode; and
storing, in a first control register, a first binary variable which indicates that the single thread may use a register set of the multiple register sets corresponding to a disabled thread of the multiple threads for the second context layer upon the rapid context switch, and a second binary variable which identifies the second register set to be used for the second context layer upon the rapid context switch in the single thread;
performing a context switch in said single-thread mode from a first context layer in the first register set executed during a first particular time range of the execution of the single thread to a second context layer in the second register set executed during a second particular time range of the execution of the single thread, in which the first register set stores data associated with the first context layer which includes state information for restoring an interrupted process, wherein performing the context switch comprises accessing the first control register, wherein the storing occurs prior to performing the context switch such that the second binary variable of the control register identifies the second register set during execution of the first context layer, prior to the context switch to the second context layer.

12. The method of claim 11 , wherein when said instruction pipeline is operating in said multi-threaded mode, the method further comprises processing multiple threads using time multiplexing.

13. The method of claim 11 , wherein said instruction pipeline is arranged to contain instructions from only one thread when in the single-thread mode.

14. The method of claim 11 , wherein said instruction pipeline is arranged to process multiple threads simultaneously.

Assignees

• Robertson Alistair
• Scott Jeffrey W
• Nxp Usa Inc

Inventors

• Robertson Alistair
• Scott Jeffrey W

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/30189 Primary

  according to execution mode, e.g. mode flag · CPC title

• G06F9/462

  with multiple register sets · CPC title

• G06F9/3891

  organised in groups of units sharing resources, e.g. clusters · CPC title

• G06F9/48

  Program initiating; Program switching, e.g. by interrupt · CPC title