Programmable CPU register hardware context swap mechanism

Patent metadata

Field	Value
Publication number	US-9619231-B2
Application number	US-201414200417-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Mar 12, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.

First claim

What is claimed is:

1. A method for performing a context switch in a central processing unit (CPU) comprising a plurality context defining register sets, wherein each set of registers having the same number of CPU registers; the method comprising:
upon occurrence of an exception automatically switching to a register set of said plurality of context defining register sets,
wherein selection of a register set of said plurality of context defining register can further be manually initiated by executing a context switch instruction; and
indicating a currently used context in a first bitfield and a most recent context selected by said instruction in a second bitfield of a context status register.

2. The method according to claim 1 , further comprising executing the context switch instruction thereby initiating a context switch.

3. The method according to claim 2 , wherein the context switch instruction is a dedicated context swap instruction.

4. The method according to claim 3 , wherein the context status register is only readable.

5. The method according to claim 2 , wherein the context status register is readable and at least the second bitfield is writable and the context switch instruction is a move data instruction that is applied to the second bitfield of the context status register for changing the content of the context status register to initiate a context switch.

6. The method according to claim 1 , further comprising assigning a plurality of priority levels to a plurality of interrupt sources.

7. The method according to claim 6 , wherein each of said plurality of register sets is assignable to an interrupt level such that upon occurrence of an interrupt a respective register set of said plurality of context defining register sets is selected by said switching unit depending on the interrupt level.

8. The method according to claim 7 , wherein an unassigned interrupt level defaults to a default register set of said plurality of context defining register sets.

9. The method according to claim 7 , wherein upon occurrence of an interrupt with an unassigned interrupt level, the current context defining register set defines the current context.

10. The method according to claim 7 , wherein if a register set is assigned to a priority level which has already been assigned to another register set, then the CPU is operable to assign the register set with a lower number to the selected priority level and unassign the respective other register set.

11. The method according to claim 7 , further comprising providing a fuse field for assigning said interrupt levels to one of said plurality of register sets.

12. The method according to claim 1 , further comprising updating the context status register with a new context in the first bitfield after a context switch has been performed.

13. The method according to claim 1 , wherein the context switch instruction comprises a literal which identifies a chosen context.

14. The method according to claim 1 , wherein the context switch instruction identifies a register which stores information identifying a chosen context.

15. A central processing unit (CPU) comprising:
an interrupt unit for interrupting execution of instructions;
a plurality of context defining register sets, wherein each set of registers having the same number of CPU registers;
a switching unit configured to couple one of the plurality of context defining register sets within the CPU, wherein the switching unit switches to a predetermined register set of said plurality of context defining register sets upon occurrence of an exception or upon execution of a context switch instruction; and
a context status register coupled with the switching unit, wherein the context status register comprises a first bitfield indicating a current context and a second bitfield indicating a most recent context selected by said context switch instruction.

16. The CPU according to claim 15 , wherein the context switch instruction is a dedicated context swap instruction.

17. The CPU according to claim 16 , wherein the context status register is only readable.

18. The CPU according to claim 15 , wherein the context status register is readable and at least the second bitfield is writable and the context switch instruction is a move data instruction that is applied to the second bitfield of the context status register for changing the content of the context status register to initiate a context switch.

19. The CPU according to claim 15 , wherein the interrupt unit comprises an interrupt controller operable to assign a plurality of priority levels to a plurality of interrupt sources.

20. The CPU according to claim 19 , wherein each of said plurality of register sets is assignable to an interrupt level such that upon occurrence of an interrupt a respective register set of said plurality of context defining register sets is selected by said switching unit depending on the interrupt level.

21. The CPU according to claim 20 , wherein an unassigned interrupt level defaults to a default register set of said plurality of context defining register sets.

22. The CPU according to claim 20 , wherein upon occurrence of an interrupt with an unassigned interrupt level the current context defining register set defines the current context.

23. The CPU according to claim 20 , wherein if a register set is assigned to a priority level which has already been assigned to another register set, then the CPU is operable to assign the register set with a lower number to the selected priority level and unassign the respective other register set.

24. The CPU according to claim 20 , further comprising a fuse field for assigning said interrupt levels to one of said plurality of register sets.

25. The CPU according to claim 15 , wherein the context status register is updated with a new context after a context switch has been performed.

26. The CPU according to claim 15 , wherein the context switch instruction comprises a literal which identifies a chosen context.

27. The CPU according to claim 15 , wherein the context switch instruction identifies a register which stores information identifying a chosen context.

Assignees

• Microchip Tech Inc

Inventors

• Catherwood Michael I
• Kris Bryan
• Mickey David
• Kanellopoulos Joseph

Classifications

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/462 Primary

  with multiple register sets · CPC title

• G06F9/3865

  using deferred exception handling, e.g. exception flags · CPC title