Lateral bipolar junction transistor with abrupt junction and compound buried oxide

Patent metadata

Field	Value
Publication number	US-10727299-B2
Application number	US-201816149598-A
Country	US
Kind code	B2
Filing date	Oct 2, 2018
Priority date	Apr 13, 2016
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.

First claim

What is claimed is:

1. A method of forming a lateral bipolar junction transistor (LBJT) comprising:
providing a germanium containing material on a nucleation dielectric layer with a bonding method, wherein the nucleation dielectric layer comprises silicon nitride or silicon oxide including implanted silicon to include nucleation sites;
patterning the germanium containing material selectively to the nucleation dielectric layer to form a base region present overlying a pedestal of the passivating layer; and
forming an emitter region and collector region on exposed portions of the nucleation dielectric layer.

2. The method of claim 1 , wherein said providing the germanium containing material on the nucleation dielectric layer with the bonding method comprises:
forming a first material stack comprising a nucleation dielectric layer, wherein the second material stack further comprises a buried oxide region separating the nucleation dielectric layer from a supporting substrate;
forming a second material stack comprising a passivating layer on said germanium containing or type III-V semiconductor material on said passivating layer, wherein the first material stack further comprises a sacrificial oxide layer separating said germanium containing material from a handling substrate;
bonding the first material stack to the second material stack through contact between the nucleation dielectric layer and the passivating layer; and
removing the handling substrate and the sacrificial oxide layer.

3. The method of claim 1 , further comprising:
forming an extrinsic base material layer comprising a doped polycrystalline silicon material, doped polycrystalline germanium containing material or a doped single crystalline germanium containing material on the germanium containing semiconductor base material;
forming a hard mask on the extrinsic base material layer;
etching the extrinsic base material layer selective to the hard mask and the germanium containing semiconductor base material to pattern an extrinsic base region;
forming a spacer on the sidewalls of said extrinsic base region; and
etching the germanium containing semiconductor base material to pattern the base region with an etch that is selective to the hard mask and the spacer.

4. The method of claim 3 , wherein said forming emitter and collector regions comprises performing an angled ion implantation to produce an emitter and collector junction on opposing sides of the base region.

5. The method of claim 4 , wherein the emitter region and collector region comprise polycrystalline material that is grown on the nucleation dielectric layer.

6. The method of claim 4 , wherein the emitter region and collector region comprise single crystalline semiconductor material that is grown on the nucleation dielectric layer.

7. The method of claim 4 , wherein the nucleation dielectric layer is selected from the group consisting of cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), yttrium oxide (Y 2 O 3 ), gadolinium oxide (Gd 2 O 3 ), europium oxide (Eu 2 O 3 ), terbium oxide (Tb 2 O 3 ), doped silicon nitride and combinations thereof.

8. The method of claim 4 , wherein the emitter region and the collector region comprise semiconductor material having a larger band gap than the base region.

9. A method of forming a lateral bipolar junction transistor (LBJT) comprising:
providing a type III-V semiconductor material that is present on a nucleation dielectric layer with a bonding method, wherein the nucleation dielectric layer comprises silicon including implanted silicon to include nucleation sites;
patterning the type III-V semiconductor base material selectively to the nucleation dielectric layer to form a base region; and
forming an emitter region and collector region on exposed portions of the nucleation dielectric layer.

10. The method of claim 9 , wherein said providing the type III-V semiconductor material on the nucleation dielectric layer with the bonding method comprises:
forming a first material stack comprising said nucleation dielectric layer, wherein the second material stack further comprises a buried oxide region separating the nucleation dielectric layer from a supporting substrate;
forming a second material stack comprising a passivating layer on said type III-V semiconductor material on said passivating layer, wherein the first material stack further comprises a sacrificial oxide layer separating said III-V semiconductor material from a handling substrate;
bonding the first material stack to the second material stack through contact between the nucleation dielectric layer and the passivating layer; and
removing the handling substrate and the sacrificial oxide layer.

11. The method of claim 9 , further comprising:
forming an extrinsic base material layer comprising a doped polycrystalline silicon material, doped polycrystalline germanium containing material or a doped single crystalline germanium containing material on a germanium containing semiconductor base material;
forming a hard mask on the extrinsic base material layer;
etching the extrinsic base material layer selective to the hard mask and the germanium containing semiconductor base material;
forming a spacer; and
etching the germanium containing semiconductor base material to pattern the base region with an etch that is selective to the hard mask and the spacer.

12. The method of claim 11 , wherein said forming emitter and collector regions comprises performing an ion implantation.

13. The method of claim 12 , wherein the emitter region and collector region comprise polycrystalline material that is grown on the nucleation dielectric layer.

14. The method of claim 12 , wherein the emitter region and collector region comprise single crystalline semiconductor material that is grown on the nucleation dielectric layer.

15. The method of claim 12 , wherein the nucleation dielectric layer is selected from the group consisting of cerium oxide (CeO 2 ), lanthanum oxide (La 2 O 3 ), yttrium oxide (Y 2 O 3 ), gadolinium oxide (Gd 2 O 3 ), europium oxide (Eu 2 O 3 ), terbium oxide (Tb 2 O 3 ), doped silicon nitride and combinations thereof.

16. The method of claim 12 , wherein the emitter region comprises semiconductor material having a larger band gap than the base region.

17. The method of claim 12 , wherein the collector region comprises semiconductor material having a larger band gap than the base region.

Assignees

• IBM
• Elpis Tech Inc

Inventors

• Chan Kevin K
• Hashemi Pouya
• Ning Tak H
• Reznicek Alexander

Classifications

• H10P72/7426

  used as a support during build up manufacturing of active devices · CPC title

• H10P14/6938

  the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title