Semiconductor devices, methods of manufacture thereof, and capacitors

Patent metadata

Field	Value
Publication number	US-10727294-B2
Application number	US-201815883746-A
Country	US
Kind code	B2
Filing date	Jan 30, 2018
Priority date	Dec 10, 2013
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

Semiconductor devices, methods of manufacture thereof, and capacitors are disclosed. In some embodiments, a semiconductor device includes a first capacitor and a protection device coupled in series with the first capacitor. A second capacitor is coupled in parallel with the first capacitor and the protection device.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of first capacitor plates over a workpiece;
forming a plurality of second capacitor plates over the workpiece and overlapping the plurality of first capacitor plates;
coupling each of the plurality of first capacitor plates to a first terminal;
coupling a protection device to each of the plurality of second capacitor plates; and
coupling each of the protection devices to a second terminal using an electrical conductor, wherein the electrical conductor comprises a conductive line extending along a first side and a second side of the protection device in a top down view of the semiconductor device, and wherein the first side and the second side are directly adjoined at a corner of at least one of the plurality of second capacitor plates.

2. The method according to claim 1 , wherein coupling the protection device comprises coupling a redundant capacitor or a fuse.

3. The method according to claim 1 , wherein the plurality of first capacitor plates and the plurality of second capacitor plates are part of a plurality of capacitors coupled together in parallel, and wherein coupling the protection device comprises coupling a protection device in series with each of the plurality of capacitors.

4. The method according to claim 1 , wherein coupling the protection device comprises coupling the protection device below the plurality of second capacitor plates, and wherein the plurality of second capacitor plates are disposed above the workpiece.

5. The method according to claim 1 , wherein coupling the protection device comprises coupling the protection device in material layers that the plurality of first capacitor plates and the plurality of second capacitor plates are formed in.

6. The method according to claim 1 , wherein coupling the protection device comprises coupling the protection device above the plurality of second capacitor plates, and wherein the plurality of second capacitor plates are disposed above the workpiece.

7. A method comprising:
disposing a capacitor in a dielectric layer, the capacitor comprising:
a plurality of first plates, each of the plurality of first plates being coupled to a first terminal and each of the plurality of first plates being located in a common first metallization layer on a common first plane;
a plurality of second plates, each of the plurality of second plates being coupled to a second terminal, each of the second plates being disposed over a respective one of the plurality of first plates and each of the plurality of second plates being located in a common second metallization layer on a common second plane; and

a protection device coupled between one of the plurality of second plates and the second terminal, wherein the protection device comprises a redundant capacitor or a fuse;
coupling the plurality of second plates to the protection device using an electrical connector, the electrical connector comprising:
a conductive element located in a third metallization layer different than the first and second metallization layers, the third metallization layer is disposed on a third plane different than the first and second planes; and
an electrically conductive via extending from the third plane to the second plane, wherein the conductive element is wider than the conductive via in a cross-sectional view; and

depositing an insulating etch-stop layer over and in direct contact with the dielectric layer, the insulating etch-stop layer being made of a different material than the dielectric layer, wherein the conductive element of the electrical connector extends through the insulating etch-stop layer.

8. The method of claim 7 , wherein the insulating etch-stop layer forms a first interface with a first top surface of the dielectric layer and a second interface with a second top surface of the dielectric layer the second interface being higher than the first interface in a cross-sectional view, the insulating etch-stop layer extending continuously from the first top surface of the dielectric layer to the second top surface of the dielectric layer.

9. The method of claim 7 , wherein the protection device is disposed along at least two adjoining sides of one of the plurality of first plates.

10. The method of claim 7 , wherein the protection device comprises a semiconductive fuse, and wherein the semiconductive fuse is coupled to a bottom surface of the plurality of first plates.

11. The method of claim 10 , wherein the semiconductive fuse electrically couples the plurality of first plates to an additional conductive element, the additional conductive element being located in the third metallization layer.

12. The method of claim 7 further comprising:
coupling the plurality of first plates to the protection device using an additional electrical connector, the additional electrical connector comprising:
an additional conductive element located in the third metallization layer; and
an additional electrically conductive via extending from the third plane to the first plane, wherein the additional conductive element is wider than the additional conductive via in a cross-sectional view.

13. The method of claim 7 further comprising disposing a capacitor dielectric between each of the plurality of first plates and each of the plurality of second plates.

14. A method comprising:
coupling a plurality of first plates in a dielectric layer to a first terminal;
coupling a plurality of second plates in the dielectric layer to a second terminal, each of the second plates overlaps one of the plurality of first plates, wherein the plurality of first plates and the plurality of second plates are comprised in a capacitor;
coupling a protection device between one of the plurality of second plates and the second terminal, wherein the protection device comprises a redundant capacitor or a fuse; and
depositing an insulating etch-stop layer over and forming:
a first interface with a first top surface of the dielectric layer; and
a second interface with a second top surface of the dielectric layer the second interface being higher than the first interface in a cross-sectional view, the insulating etch-stop layer extending continuously from the first top surface of the dielectric layer to the second top surface of the dielectric layer.

15. The method according to claim 14 , wherein the protection device comprises a fuse, and wherein the fuse comprises a portion of a conductive line, a conductive via, or a segment comprising a semiconductor material.

16. The method according to claim 14 , wherein the capacitor comprises a metal-insulator-metal (MIM) capacitor, and wherein the method further comprises forming the capacitor in a plurality of metallization layers of a semiconductor device.

17. The method according to claim 14 , wherein the capacitor includes about 1,000 or more of the plurality of first plates or the plurality of second plates.

18. The method according to claim 14 , wherein the capacitor comprises a decoupling capacitor.

19. The method according to claim 14 , wherein pairs of the plurality of first plates and the plurality of second plates define a plurality of capacitive units, and wherein the method further comprises adapting the protection device to self-diagnose and isolate a defaulted one of the plurality of capacitive units.

20. The method according to claim 14 further comprising:
forming a first plurality of conductive vias extending through the insulating

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiou Wen-Chih
• Jeng Shin-Puu
• Liao Ebin

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title