Semiconductor devices, methods of manufacture thereof, and capacitors

Patent metadata

Field	Value
Publication number	US-9899467-B2
Application number	US-201314102268-A
Country	US
Kind code	B2
Filing date	Dec 10, 2013
Priority date	Dec 10, 2013
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Semiconductor devices, methods of manufacture thereof, and capacitors are disclosed. In some embodiments, a semiconductor device includes a first capacitor and a protection device coupled in series with the first capacitor. A second capacitor is coupled in parallel with the first capacitor and the protection device.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first capacitor, the first capacitor including a bottom capacitor plate formed in a first metallization layer and a top capacitor plate formed in a second metallization layer, the second metallization layer being above the first metallization layer, the bottom capacitor plate and top capacitor plate each having a major surface extending along a first plane;
a protection device coupled in series with the first capacitor by an electrical connection, the electrical connection including at least one conductive element having an elongated axis that is perpendicular to the first plane;
a second capacitor coupled in parallel with the first capacitor and the protection device; and
a dielectric layer over and extending along sidewalls of the first capacitor; and
an insulating etch-stop layer over and forming a first interface with a first top surface of the dielectric layer and a second interface with a second top surface of the dielectric layer, the second interface being higher than the first interface in a cross-sectional view, the insulating etch-stop layer extending continuously from the first top surface of the dielectric layer to the second top surface of the dielectric layer.

2. The semiconductor device according to claim 1 , wherein the protection device comprises a third capacitor comprising a second bottom capacitor plate formed in the first metallization layer and a second top capacitor plate formed in the second metallization layer.

3. The semiconductor device according to claim 1 , wherein the protection device comprises a fuse.

4. The semiconductor device according to claim 3 , wherein the fuse comprises a first conductive line, wherein the first conductive line is disposed between a second conductive line and a third conductive line along a first line, wherein the first conductive line has a first dimension measured along a second line perpendicular to the first line, wherein the second conductive line has a second dimension measured along the second line, and wherein the first dimension is smaller than the second dimension.

5. The semiconductor device according to claim 3 , wherein the fuse comprises a conductive via having a higher resistance than the top capacitor plate.

6. The semiconductor device according to claim 3 , wherein the fuse comprises a semiconductive material disposed below the first capacitor.

7. The semiconductor device according to claim 1 , wherein the protection device comprises a first protection device, further comprising a second protection device coupled in series with the second capacitor, and wherein the second capacitor and the second protection device are coupled in parallel with the first capacitor and the first protection device.

8. A semiconductor device, comprising:
a capacitor comprising:
a plurality of first plates, each of the plurality of first plates being coupled to a first terminal and each of the plurality of first plates being located in a common first metallization layer on a common first plane;
a plurality of second plates, each of the plurality of second plates being coupled to a second terminal, each of the second plates being disposed opposed to a respective one of the plurality of first plates and each of the plurality of second plates being located in a common second metallization layer on a common second plane;
a protection device coupled between one of the plurality of second plates and the second terminal, wherein the protection device comprises a redundant capacitor or a fuse;
an electrical connector connecting the one of the plurality of second plates to the protection device, the electrical connector including (a) a conductive element located in a third metallization layer different than the first and second metallization layers, the third metallization layer on a third plane different than the first and second planes, and (b) an electrically conductive via extending from the second plane to the third plane, wherein the conductive element is wider than the conductive via in a cross-sectional view;

a dielectric layer over and extending along sidewalls of the capacitor; and
an insulating etch-stop layer over and in direct contact with the dielectric layer, the insulating etch-stop layer being made of a different material than the dielectric layer, wherein the conductive element of the electrical connector extends through the insulating etch-stop layer.

9. The semiconductor device according to claim 8 , wherein the protection device comprises a fuse, and wherein the fuse comprises a portion of a conductive line, a conductive via, or a segment comprising a semiconductive material.

10. The semiconductor device according to claim 8 , wherein the capacitor comprises a metal-insulator-metal (MIM) capacitor, and wherein the capacitor is formed in a plurality of metallization layers of the semiconductor device.

11. The semiconductor device according to claim 8 , the capacitor having an overall length or width in a top view of at least three hundred μm, and wherein the protection device prevents failure of the capacitor.

12. The semiconductor device according to claim 8 , wherein the capacitor includes about 1,000 or more of the plurality of first plates or the plurality of second plates.

13. The semiconductor device according to claim 8 , wherein the capacitor comprises a decoupling capacitor.

14. The semiconductor device according to claim 8 , wherein pairs of the plurality of first plates and the plurality of second plates comprise a plurality of capacitive units, and wherein the protection device is adapted to self-diagnose and isolate a defaulted one of the plurality of capacitive units.

15. A semiconductor device, comprising:
a plurality of first capacitor plates over a workpiece, each of the plurality of first capacitor plates being coupled to a first terminal and each of the plurality of first capacitor plates being in a common plane;
a plurality of second capacitor plates over the workpiece and parallel to the plurality of first capacitor plates, each of the plurality of second capacitor plates being in a common second plane different than the common plane; and
a plurality of protection devices connected to a second terminal through a plurality of conductive elements each extending in a direction perpendicular to the common second plane, the plurality of protection devices being coupled to at least one of the second capacitor plates by one or more electrical connectors, wherein the one or more electrical connectors comprises a conductive line extending along a first side and a second side of the at least one second capacitor plate in a top down view of the semiconductor device, and wherein the first side and the second side are directly adjoined at a corner of the at least one second capacitor plate, wherein the plurality of protection devices comprises:
a plurality of third capacitor plates disposed in the common plane; and
a plurality of fourth capacitor plates disposed in the common second plane.

16. The semiconductor device according to claim 15 , wherein the plurality of first capacitor plates and the plurality of second capacitor plates comprise a plurality of capacitors coupled together in parallel, and wherein one of the plurality of protection devices is coupled in series with each of the plurality of second capacitor plates.

17. The semiconductor device according to claim 15 , wherein the plurality of first capacitor plates and the plurality of second capacitor plates are formed in material layers, and wherein the plurality of protection d

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiou Wen Chih
• Jeng Shin Puu
• Liao Ebin

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/5223

  Electricity · mapped topic