Flip-flop including 3-state inverter

Patent metadata

Field	Value
Publication number	US-10720909-B2
Application number	US-201916522835-A
Country	US
Kind code	B2
Filing date	Jul 26, 2019
Priority date	Jul 14, 2016
Publication date	Jul 21, 2020
Grant date	Jul 21, 2020

Abstract

A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

First claim

What is claimed is:

1. A flip-flop comprising:
at least one first fin;
at least one second fin parallel with the at least one first fin;
a first power contact and a second power contact on the at least one first fin;
a first ground contact and a second ground contact on the at least one second fin;
first and second gate patterns on the at least one first fin and the at least one second fin between the first and second power contacts and between the first and second ground contacts;
third and fourth gate patterns on the at least one first fin between the first and second gate patterns;
fifth and sixth gate patterns on the at least one second fin between the first and second gate patterns;
first, second and third contacts on the first gate pattern, the third gate pattern and the fifth gate pattern respectively;
a fourth contact on the at least one first fin between the third and fourth gate patterns;
a fifth contact on the at least one second fin between the fifth and sixth gate patterns; and
sixth, seventh and eighth contacts on the fourth gate pattern, the sixth gate pattern and the second gate pattern respectively.

2. The flip-flop of claim 1 , wherein the second contact and the seventh contact is configured to receive a first clock signal, and
the third contact and the sixth contact is configured to receive a second clock signal.

3. The flip-flop of claim 1 , further comprising:
a seventh gate pattern on the at least one first fin and the at least one second fin;
a ninth contact on the seventh gate pattern;
a tenth contact on the at least one first fin;
a eleventh contact on the at least one second fin,
wherein the second power contact and the second ground contact are between the second gate pattern and the seventh gate pattern,
the seventh gate pattern is between the second power contact and the tenth contact and between the second ground contact and the eleventh contact, and
the tenth contact and the eleventh contact are electrically connected each other.

4. The flip-flop of claim 3 , wherein the eighth contact is electrically connected to the tenth contact and the eleventh contact.

5. The flip-flop of claim 3 , wherein the fourth contact and the fifth contact is electrically connected to the ninth contact.

6. The flip-flop of claim 3 , further comprising:
a master latch configured to output signal to the first contact,
wherein the first gate pattern, the third gate pattern and the fifth gate pattern are a portion of an inverter configured to invert the signal received at the first contact and output the inverted signal to the fourth contact and the fifth contact, and
the second gate pattern, the fourth gate pattern, the sixth gate pattern and the seventh gate pattern are a portion of a slave latch configured to store the signal by inverting the inverted signal received at the fourth contact and the fifth contact, and output the stored signal at the tenth contact and the eleventh contact.

7. The flip-flop of claim 3 , further comprising:
an eighth gate pattern on the at least one first fin and the at least one second fin, wherein the tenth contact and the eleventh contact are between the seventh gate pattern and the eighth gate pattern.

8. The flip-flop of claim 1 , wherein the at least one first fin comprises a first P-type fin and a second P-type fin, and
the at least one second fin comprises a first N-type fin and a second N-type fin.

9. The flip-flop of claim 1 , wherein a number of the at least one first fin between the first power contact and the second power contact is equal to a number of the at least one second fin between the first ground contact and the second ground contact.

10. The flip-flop of claim 1 , further comprising:
a seventh gate pattern on the at least one first fin between the first power contact and the second power contact; and
a jumper on the seventh gate pattern and electrically connecting portions of the at least one first fin separated by the seventh gate pattern.

11. The flip-flop of claim 1 , further comprising:
a seventh gate pattern on the at least one second fin between the first ground contact and the second ground contact; and
a jumper on the seventh gate pattern and electrically connecting portions of the at least one second fin separated by the seventh gate pattern.

12. The flip-flop of claim 1 , wherein the fourth and fifth contacts being electrically connected each other.

13. An apparatus comprising:
at least one P-type fin;
at least one N-type fin parallel with the at least one P-type fin;
a first power contact and a second power contact on the at least one P-type fin;
a first ground contact and a second ground contact on the at least one N-type fin;
first and second gate patterns on the at least one P-type fin and the at least one N-type fin between the first and second power contacts and between the first and second ground contacts;
third and fourth gate patterns on the at least one P-type fin between the first and second gate patterns;
fifth and sixth gate patterns on the at least one N-type fin between the first and second gate patterns;
first, second and third contacts on the first gate pattern, the third gate pattern and the fifth gate pattern respectively;
a fourth contact on the at least one P-type fin between the third and fourth gate patterns;
a fifth contact on the at least one N-type fin between the fifth and sixth gate patterns;
sixth, seventh and eighth contacts on the fourth gate pattern, the sixth gate pattern and the second gate pattern respectively.

14. The apparatus of claim 13 , wherein the fourth and fifth contacts being electrically connected each other.

15. A flip-flop comprising:
at least one first fin;
at least one second fin parallel with the at least one first fin;
a first power contact and a second power contact on the at least one first fin;
a first ground contact and a second ground contact on the at least one second fin;
first, second, third and fourth gate patterns on the at least one first fin between the first power contact and the second power contact;
fifth to eighth gate patterns on the at least one second fin between the first ground contact and the second ground contact;
a ninth gate pattern on the at least one first fin and a tenth gate pattern on the at least one second fin;
a first contact connected to the first gate pattern and the fifth gate pattern;
second and third contacts connected to the second and sixth gate patterns respectively;
a fourth contact connected to the at least one first fin between the second and third gate patterns;
a fifth contact connected to the at least one second fin between the sixth and seventh gate patterns;
sixth and seventh contacts connected to the third and seventh gate patterns respectively;
an eighth contact connected to the fourth and eighth gate patterns;
a ninth contact connected to ninth and tenth gate patterns, the ninth contact being electrically connected to the fourth and fifth contacts; and
tenth and eleventh contacts connected to the at least one first fin and the at least one second fin respectively,
wherein the ninth gate pattern is between the second power contact and the tenth contact, and
the tenth gate pattern is between the second ground contact and the eleventh contact.

16. The flip-flop of claim 15 , wherein the fifth contact being electrically connected to the fourth contact, and
the tenth and eleventh contacts being electrically connected to the eighth contact.

17. The flip-flop of claim 15 , wherein the first gate pattern, the second gate p

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ha-Young
• Lee Dalhee
• Oh Hyoung-Suk
• Lee keunho
• Song Taejoong
• Cho Sungwe

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H03K3/35625 Primary

  using complementary field-effect transistors · CPC title

• H03K3/356104 Primary

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H03K23/001

  using elements not covered by groups H03K23/002 and H03K23/74 - H03K23/84 · CPC title