Low power clock gated flip-flops

Patent metadata

Field	Value
Publication number	US-9331680-B2
Application number	US-201414481992-A
Country	US
Kind code	B2
Filing date	Sep 10, 2014
Priority date	Sep 10, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A flip-flop that includes a multiplexer configured to generate a multiplexer output. The multiplexer output is generated in response to an input and a scan enable, and is given to a transmission gate. A master latch is coupled to the transmission gate and to a tri-state inverter. The master latch is configured to receive an output of the transmission gate. A slave latch is configured to receive an output of the tri-state inverter and the multiplexer output. A data inverter is coupled to the slave latch. The data inverter is configured to generate a flip-flop output. A half clock gating inverter is configured to generate an inverted clock input in response to a clock input and the multiplexer output.

First claim

What is claimed is:

1. A flip-flop comprising:
a multiplexer configured to generate a multiplexer output to a transmission gate, in response to at least one input and a scan enable;
a master latch configured to receive an output of the transmission gate;
a tri-state inverter configured to receive an output of the master latch;
a slave latch configured to receive an output of the tri-state inverter and the multiplexer output;
a data inverter coupled to an output of the slave latch, configured to generate a flip-flop output; and
a half clock gating inverter configured to generate an inverted clock input in response to a clock input and the multiplexer output.

2. The flip-flop of claim 1 , wherein the half clock gating inverter comprises:
an inverter having a first PMOS transistor and a first NMOS transistor, receiving the clock input to generate the inverted clock input;
a second PMOS transistor coupled to a source of the first PMOS transistor, a gate of the second PMOS transistor configured to be controlled by the multiplexer output; and
a second NMOS transistor coupled to a node between the drains of the first PMOS transistor and the first NMOS transistor, a gate of the second NMOS transistor configured to be controlled by the multiplexer output.

3. The flip-flop of claim 2 , wherein:
the second PMOS transistor is activated and the second NMOS transistor is inactivated when the multiplexer output is logic ‘0’, thereby generating the inverted clock input; and
the second PMOS transistor is inactivated and the second NMOS transistor is activated when the multiplexer output is logic ‘1’, thereby tying the inverted clock input to logic ‘0’.

4. The flip-flop of claim 1 , wherein the at least one input comprises a data input and a scan data input; and wherein, the multiplexer receives the data input, the scan data input, the scan enable and an inverted scan enable and is configured to select one of the data input and the scan data input in response to the scan enable.

5. The flip-flop of claim 1 , wherein the master latch comprises a first plurality of back-to-back connected inverters and wherein, the first plurality of back-to-back connected inverters comprises an inverter coupled to a tri-state inverter.

6. The flip-flop of claim 1 , wherein:
the slave latch comprises a second plurality of back-to-back connected inverters, wherein the second plurality of back-to-back connected inverters comprises a first inverter coupled to a second tri-state inverter;
the first inverter of the second plurality of back-to-back connected inverter is configured to generate an output to the data inverter; and
a third NMOS transistor coupled in parallel to an NMOS transistor of the second tri-state inverter, a gate of the third NMOS transistor receiving the multiplexer output, a gate of the NMOS transistor of the second tri-state inverter configured to receive the inverted clock.

7. The flip-flop of claim 6 , wherein in the slave latch:
the third NMOS transistor is inactivated when the multiplexer output is logic ‘0’; and
the third NMOS transistor of the slave latch is configured to store the multiplexer output when the data input is logic ‘0’ and the clock input is logic ‘0’.

8. The flip-flop of claim 1 , wherein:
a data output is generated at the flip-flop output in a data state when the scan enable is logic ‘0’; and
a scan data output is generated at the flip-flop output in a scan state when the scan enable is logic ‘1’.

9. The flip-flop of claim 1 , further comprising:
a scan inverter, configured to receive the scan enable to generate the inverted scan enable.

10. An apparatus comprising:
a clock input;
a plurality of flip-flops configured to receive the clock input; wherein each of the flip-flops comprises:
a multiplexer configured to generate a multiplexer output to a transmission gate, in response to an input and a scan enable;
a master latch configured to receive an output of the transmission gate;
a tri-state inverter configured to receive an output of the master latch;
a slave latch configured to receive an output of the tri-state inverter and the multiplexer output;
a data inverter coupled to an output of the slave latch, configured to generate a flip-flop output; and
a half clock gating inverter configured to generate an inverted clock input in response to the clock input and the multiplexer output; wherein the half clock gating inverter comprises:
a first PMOS and a first NMOS transistor, both configured to receive the clock input at gate terminal and configured to generate the inverted clock input;
a second PMOS transistor coupled to a source of the first PMOS transistor, the second PMOS transistor configured to be controlled by the multiplexer output; and
a second NMOS transistor coupled to a node between the drains of the first PMOS transistor and the first NMOS transistor, the second NMOS transistor configured to be controlled by the multiplexer output.

Assignees

• Texas Instruments Inc

Inventors

• Gurumurthy Girishankar
• Vasishta Mahesh Ramdas

Classifications

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K3/35625 Primary

  using complementary field-effect transistors · CPC title