Buffer, and multiphase clock generator, semiconductor apparatus and system using the same
US-9847775-B2 · Dec 19, 2017 · US
US9148149B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9148149-B2 |
| Application number | US-201414176025-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 7, 2014 |
| Priority date | Mar 25, 2013 |
| Publication date | Sep 29, 2015 |
| Grant date | Sep 29, 2015 |
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A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse tri-state gate may be coupled to the output of the tri-state gate via a second undoped polysilicon strip.
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The invention claimed is: 1. A latch circuit, comprising: a tri-state gate having an input, an output, and receiving complementary control signals; a reverse tri-state gate having an input, an output, and sharing the complementary control signals with the tri-state gate, wherein the reverse tri-state gate is configured to lock an output of the tri-state gate when the tri-state gate is shut-off; a first undoped polysilicon strip for generating one of the complementary control s…
Electricity · mapped topic
Electricity · mapped topic
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