Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9502410-B1
Application number	US-201514792591-A
Country	US
Kind code	B1
Filing date	Jul 6, 2015
Priority date	Jun 9, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate having a first fin structure and a second fin structure disposed thereon;
a first isolation region located between the first fin structure and the second fin structure;
a second isolation region located opposite the first fin structure from the first isolation region; and
at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.

2. The semiconductor structure of claim 1 , further comprising at least one gate structure crossing over the first fin structure and the second fin structure.

3. The semiconductor structure of claim 2 , wherein the gate structure covers the first fin structure asymmetrically.

4. The semiconductor structure of claim 2 , wherein at least one gate structure comprises two epitaxial layers disposed on two sides of the gate structure respectively, wherein the two epitaxial layers have different volumes.

5. The semiconductor structure of claim 1 , wherein the depth of the second isolation region is larger than the depth of the first isolation region.

6. The semiconductor structure of claim 1 , wherein the bottom surface of the epitaxial layer is a flat surface, and the epitaxial layer further comprises two sidewalls.

7. The semiconductor structure of claim 6 , wherein the angle between the flat surface and one of the sidewall is larger than 90 degrees.

8. The semiconductor structure of claim 1 , wherein the bottom surface of the epitaxial layer has an angle.

Assignees

• United Microelectronics Corp

Inventors

• Feng li-wei
• Tsai Shih-Hung
• Liu Hon-Huei
• Lin Chao-Hung
• Huang Nan-Yuan
• Jenq Jyh-Shyang

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title