Method of fabricating tunneling transistor

Patent metadata

Field	Value
Publication number	US-10707305-B2
Application number	US-201916354126-A
Country	US
Kind code	B2
Filing date	Mar 14, 2019
Priority date	Jul 18, 2016
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

First claim

What is claimed is:

1. A method of forming a tunneling transistor, comprising:
forming a fin shaped structure in a substrate;
forming a gate structure across the fin shaped structure;
forming a first recess on one side of the gate structure formed across the fin shaped structure, and forming a second recess on an another side of the gate structure formed across the fin shaped structure, wherein the first recess comprises a sidewall having a first edge inclined toward the gate structure, and the second recess comprises a sidewall having a first edge inclined toward the gate structure;
forming a source structure in the first recess; and
forming a drain structure in the second recess, an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials, wherein the source structure comprises SiGe with a concentration of Ge therein being gradually decreased along a direction away from a channel region, and the drain structure comprises SiP with a concentration of C therein being gradually decreased along another direction away from the channel region.

2. The method of forming a tunneling transistor according to claim 1 , wherein the gate structure comprises a spacer and the first edge of the sidewall of the first recess or the sidewall of the second recess is formed under the spacer.

3. The method of forming a tunneling transistor according to claim 1 , wherein the first recess is formed through a first dry etching process, and wherein the second recess is formed through a second dry etching process.

4. The method of forming a tunneling transistor according to claim 1 , further comprising:
performing an ion implanting process before the source structure and the drain structure are formed, to form a doped region on surfaces of the sidewall.

5. The method of forming a tunneling transistor according to claim 1 , further comprising:
performing a first in situ doping process while the source structure is formed, and performing a second in situ doping process while the drain structure is formed.

6. The method of forming a tunneling transistor according to claim 1 , wherein the source structure is formed in the first recess before the second recess is formed.

Assignees

• United Microelectronics Corp

Inventors

• Chen Cheng-Guo
• Wu Kun-Yuan
• Chen Tai-You
• Ho Chiu-Sheng
• Yang Po-Kang
• Lo Ta-Kang

Classifications

• H10D62/82

  Heterojunctions · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D62/822 Primary

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D62/021

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title