Metal gates for semiconductor devices and method thereof
US-2024429281-A1 · Dec 26, 2024 · US
Tunneling transistor
US8933435B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8933435-B2 |
| Application number | US-201213727547-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 26, 2012 |
| Priority date | Dec 26, 2012 |
| Publication date | Jan 13, 2015 |
| Grant date | Jan 13, 2015 |
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Abstract
Official abstract text for this publication.
Devices and methods for forming a device are presented. The device includes a substrate and a fin type transistor disposed on the substrate. The transistor includes a fin structure which serves as a body of the transistor. The fin structure includes first and second end regions and an intermediate region in between the first and second end regions. A source region is disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure. The device includes a channel region disposed adjacent to the source region and a gate dielectric of the gate. A source tunneling junction is aligned to the gate with a controlled channel thickness T CH .
First claim
Opening claim text (preview).
What is claimed is: 1. A device comprising: a substrate; and a fin-type transistor disposed on the substrate, wherein the transistor comprises a fin structure which serves as a body of the transistor, wherein the fin structure includes first and second end regions and an intermediate region in between the first and second end regions of the fin structure, a source region disposed on the first end region, a drain region disposed in the second end region and a gate disposed on t…
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Classifications
Electricity · mapped topic
- H10D64/017Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/6211Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8933435B2 cover?
- Devices and methods for forming a device are presented. The device includes a substrate and a fin type transistor disposed on the substrate. The transistor includes a fin structure which serves as a body of the transistor. The fin structure includes first and second end regions and an intermediate region in between the first and second end regions. A source region is disposed on the first end r…
- Who is the assignee on this patent?
- Univ Singapore, Globalfoundries Sg Pte Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D64/017. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 13 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).