Package with vertical interconnect between carrier and clip

Patent metadata

Field	Value
Publication number	US-10707158-B2
Application number	US-201715497267-A
Country	US
Kind code	B2
Filing date	Apr 26, 2017
Priority date	Apr 27, 2016
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

First claim

What is claimed is:

1. A package, comprising:
a chip carrier;
an electronic chip on the chip carrier;
a clip on the electronic chip;
an encapsulant at least partially encapsulating the electronic chip;
an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip, wherein the electronic chip and the connection structure are arranged side by side between the chip carrier and the clip and are spaced apart from each other by a void space,
wherein the void space between the electrically conductive vertical connection structure and the electronic chip is filled by the encapsulant,
wherein both the chip carrier and the clip have at least a surface portion exposed with regard to the encapsulant,
wherein the surface portion of the chip carrier onto which the electronic chip is arranged is a planar surface,
wherein the connection structure is a structure being separate from the clip and the chip carrier,
wherein a surface portion of the clip being connected to the chip and the connection structure is a planar surface such that the connection structure bridges the distance between the planar surface portion of the clip being connected to the chip and the connection structure and the planar surface portion of the chip carrier onto which the electronic chip is arranged,
wherein the electronic chip has at least one chip pad on a main surface of the chip,
wherein the chip pad is covered with a solderable interconnect,
wherein the pad, the solderable interconnect and the complete main surface are embedded in a dielectric layer while keeping the solderable interconnect uncovered, so as to provide a further planar surface for abutting the planar surface portion of the clip.

2. The package according to claim 1 , wherein the electronic chip is electrically connected to at least one of the chip carrier and the clip.

3. The package according to claim 1 wherein the solderable interconnect is at least one of a diffusion solder material and a sintering paste.

4. A semifinished product composed of a plurality of preforms of packages, the semifinished product comprising:
a batch carrier comprising a plurality of chip carrier sections;
a plurality of electronic chips arranged on the batch carrier so that each of the electronic chips is assigned to a respective one of the chip carrier sections;
a batch clip comprising a plurality of clip sections and being arranged on the electronic chips so that each of the electronic chips is assigned to a respective one of the clip sections;
a plurality of electrically conductive vertical connection structures provided separately from the batch clip, wherein each of the connection structures electrically connects a respective one of the chip carrier sections with a respective one of the clip sections,
wherein at least one of the plurality of electronic chips and at least one of the plurality of connection structures are arranged side by side between the at least one of the chip carrier section and the one of the plurality of clips and are spaced apart from each other by a void space,
an encapsulant encapsulating at least partially the electronic chips, the batch clip and the batch carrier,
wherein the void space between the electrically conductive vertical connection structures and the electronic chip is filled by the encapsulant,
wherein both the chip carriers and the clips have at least a surface portion exposed with regard to the encapsulant,
wherein the surface portion of the batch chip carrier onto which the electronic chips are arranged is a planar surface,
wherein the connection structures are a structure being separate from the batch clip and the batch chip carrier,
wherein a surface portion of the batch clip sections being connected to the respective chips and the connection structures is a planar surface such that the connection structures bridge the distance between the planar surface portions of the batch clip sections being connected to the chip and the connection structures and the planar surface portion of the batch chip carrier onto which the electronic chips are arranged,
wherein each of the electronic chips has at least one chip pad on a respective main surface of the chip,
wherein the chip pad is covered with a solderable interconnect,
wherein the pad, the solderable interconnect and the complete main surface are embedded in a dielectric layer while keeping the solderable interconnect uncovered, so as to provide a further planar surface for abutting the planar surface portion of the clip.

5. The semifinished product according to claim 4 , wherein the batch clip is configured as a substantially two-dimensional electrically conductive sheet.

6. The semifinished product according to claim 4 , wherein at least one of the batch carrier and the batch clip has a dimension of at least 100 cm 2 , in particular of at least 1000 cm 2 .

7. The semifinished product according to claim 4 , wherein at least one of the batch carrier and the batch clip is free of undercuts.

8. The semifinished product according to claim 4 , wherein the batch clip has a profiled surface facing the electronic chips and has an opposing planar surface.

9. The semifinished product according to claim 4 , wherein the batch carrier has a profiled surface.

10. A method of manufacturing a package, the method comprising:
mounting an electronic chip on a chip carrier;
mounting a clip on the electronic chip;
electrically connecting the chip carrier with the clip by an electrically conductive vertical connection structure provided separately from the clip; and
at least partially encapsulating the electronic chip by an encapsulant, wherein the electronic chip and the connection structure are arranged side by side between the chip carrier and the clip and are spaced apart from each other by a void space,
wherein the void space between the electrically conductive vertical connection structure and the electronic chip is filled by the encapsulant,
wherein both the chip carrier and the clip have at least a surface portion exposed with regard to the encapsulant,
wherein the surface portion of the chip carrier onto which the electronic chip is arranged is a planar surface,
wherein the connection structure is a structure being separate from the clip and the chip carrier,
wherein a surface portion of the clip being connected to the chip and the connection structure is a planar surface such that the connection structure bridges the distance between the planar surface portion of the clip being connected to the chip and the connection structure and the planar surface portion of the chip carrier onto which the electronic chip is arranged,
wherein the electronic chip has at least one chip pad on a main surface of the chip,
covering the chip pad with a solderable interconnect,
embedding the pad, the solderable interconnect and the complete main surface in a dielectric layer while keeping the solderable interconnect uncovered, so as to provide a further planar surface for abutting the planar surface portion of the clip.

11. The method according to claim 10 , wherein the connecting is accomplished by the application of at least one of mechanical pressure and heat.

12. A method of manufacturing a batch of packages, the method comprising:
providing a batch carrier comprising a plurality of chip carrier sections;
arranging a plurality of electronic chips on the batch carrier so that each of the electronic chips is assigned to a respective one of the chip carrier sections;
arranging a batch clip, which comprises a plurality of clip sections, on the electronic chips so that each of

Assignees

• Infineon Technologies Ag

Inventors

• Heinrich Alexander
• Goller Bernd
• Meyer Thorsten
• Ofner Gerald

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/796

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W80/334

  Thermocompression bonding · CPC title