Apparatuses for integrating arithmetic with logic operations

Patent metadata

Field	Value
Publication number	US-10705840-B2
Application number	US-201916452868-A
Country	US
Kind code	B2
Filing date	Jun 26, 2019
Priority date	Jun 27, 2017
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

An apparatus integrates arithmetic with logic operations. The apparatus includes a calculation device that calculates source data to generate and output first destination data. The apparatus further includes a normalization unit, coupled to the calculation device, that normalizes the first destination data to generate second destination data of a first type when receiving a signal indicating an output of first-type data, and normalizing the first destination data to generate the second destination data of a second type when receiving the signal indicating an output of second-type data.

First claim

What is claimed is:

1. An apparatus for integrating arithmetic with logic operations, comprising:
a calculation device, calculating source data to generate and output first destination data; and
a normalization unit, coupled to the calculation device, normalizing the first destination data to generate second destination data of a first type when receiving a signal indicating an output of first-type data, and normalizing the first destination data to generate the second destination data of a second type when receiving the signal indicating an output of second-type data;
wherein the normalization unit comprises:
a shifter;
an adder;
a comparator, coupled to the shifter and the adder, wherein the comparator, the shifter and the adder form a loop for performing a normalization of a floating-point value; and
a merger, coupled to the shifter and the adder, combining a sign bit, a mantissa output from the shifter and an exponent output from the adder to generate the second destination data.

2. The apparatus of claim 1 , wherein the normalization unit is coupled to the calculation device via a delay circuit,
wherein the calculation device generates and outputs the first destination data at one cycle and the normalization unit normalizes the first destination data to generate the second destination data of the first type or the second type at the next cycle.

3. The apparatus of claim 1 , wherein the calculation device performs a calculation:
dest=Src 0 ×Src 1 +Src 2 ,

Src 0 , Src 1 and Src 2 represent the source data of three source memories, and dest represents the first destination data.

4. The apparatus of claim 1 , wherein the second destination data of the first type is 24-bit floating-point value, and the second destination data of the second type is 32-bit floating-point value.

5. The apparatus of claim 1 , wherein the shifter drops 7 bits from a mantissa of 34 bits of the first destination data and the adder drops 1 bit from an exponent of 10 bits of the first destination data when receiving the signal indicating an output of first-type data.

6. The apparatus of claim 5 , wherein the comparator repeatedly operates until the MSB (Most Significant Bit) of a output from the shifter is 1,
wherein, in each iteration, when the MSB of the output of the shifter is not 1, the comparator directs the shifter to left-shift the mantissa of the first destination data by one bit and directs the adder to add −1 to the exponent of the first destination data.

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Zhang Huaisheng
• Liang Dacheng
• Chen Boming
• Bian Renyu

Classifications

• G06F9/30038

  using a mask · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title