Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage

Patent metadata

Field	Value
Publication number	US-9740484-B2
Application number	US-201113995494-A
Country	US
Kind code	B2
Filing date	Dec 22, 2011
Priority date	Dec 22, 2011
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving the bits identified by the start bit address and number of bits from a bit-oriented register or cache; and performing a sequence of specified bit operations on the retrieved bits to generate results.

First claim

We claim:

1. A method comprising:
executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved;
determining whether the bits identified by the start bit address and number of bits are stored in a bit-oriented register or cache;
when not, then determining a start byte address and a number of bytes to be retrieved form a byte-oriented memory by converting the start bit address and the number of bits identified by the instruction to the start byte address and the number of bytes respectively;
retrieving the bytes identified by the start byte address and the number of bytes from the byte-oriented memory;
discarding unwanted bits from at least one of the first byte and the last byte retrieved from the byte-oriented memory, wherein discarding the unwanted bits includes bit shifting; and
performing a sequence of specified bit operations on the remaining bits after the bit shifting to generate results.

2. The method as in claim 1 further comprising:
generating a byte address for storing the results back to the byte-oriented memory; and
using the byte address to store the results back to the byte-oriented memory.

3. The method as in claim 1 wherein the sequence of specified bit operations is a part of a decompression process for decompressing a bit stream.

4. A method comprising:
executing an instruction to put new bits for an operation into a bit stream, the instruction identifying a start bit address, a number of bits, and bits to be processed;
determining whether the bits identified by the start bit address and number of bits are stored in a bit-oriented register or cache;
when not, then determining a start byte address and a number of bytes to be retrieved from a byte-oriented memory by converting the start bit address and the number of bits identified by the instruction to the start byte address and the number of bytes respectively;
retrieving the bytes identified by the start byte address and the number of bytes from the byte-oriented memory;
discarding unwanted bits from at least one of the first byte and the last byte retrieved from the byte-oriented memory, wherein discarding the unwanted bits includes bit shifting;
performing a sequence of specified bit operations on the remaining bits after the bit shifting and the new bits to generate results; and
storing the results back to the bit-oriented register or cache.

5. The method as in claim 4 further comprising:
generating a byte address for storing the results back to the byte-oriented memory; and
using the byte address to store the results back to the byte-oriented memory.

6. The method as in claim 4 wherein the sequence of specified bit operations is a part of a compression process for compressing a bit stream.

7. A non-transitory machine-readable storage medium containing instructions, which when executed by a processor, causes the processor to perform the operations of:
executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved;
determining whether the bits identified by the start bit address and number of bits are stored in a bit-oriented register or cache;
when not, then determining a start byte address and a number of bytes to be retrieved from a byte-oriented memory by converting the start bit address and the number of bits identified by the instruction to the start byte address and the number of bytes respectively;
retrieving the bytes identified by the start byte address and the number of bytes from the byte-oriented memory;
discarding unwanted bits from at least one of the first byte and the last byte retrieved from the byte-oriented memory, wherein discarding the unwanted bits includes bit shifting; and
performing a sequence of specified bit operations on the remaining bits after the bit shifting to generate results.

8. The non-transitory machine-readable storage medium as in claim 7 performing the additional operations of:
generating a byte address for storing the results back to the byte-oriented memory; and
using the byte address to store the results back to the byte-oriented memory.

9. The non-transitory machine-readable storage medium as in claim 7 wherein the sequence of specified bit operations is a part of a decompression process for decompressing a bit stream.

10. A non-transitory machine-readable storage medium containing instructions, which when executed by a processor, causes the processor to perform the operations of:
executing an instruction to put new bits for an operation into a bit stream, the instruction identifying a start bit address, a number of bits, and bits to be processed;
determining whether the bits identified by the start bit address and number of bits are stored in a bit-oriented register or cache;
when not, then determining a start byte address and a number of bytes to be retrieved from a byte-oriented memory by converting the start bit address and the number of bits identified by the instruction to the start byte address and the number of bytes respectively;
retrieving the bytes identified by the start byte address and the number of bytes from the byte-oriented memory;
discarding unwanted bits from at least one of the first byte and the last byte retrieved from the byte-oriented memory, wherein discarding the unwanted bits includes bit shifting; and
performing a sequence of specified bit operations on the remaining bits after the bit shifting and the new bits to generate results.

11. The non-transitory machine-readable storage medium as in claim 10 performing the additional operations of:
generating a byte address for storing the results back to the byte-oriented memory; and
using the byte address to store the results back to the byte-oriented memory.

12. The non-transitory machine-readable storage medium as in claim 10 wherein the sequence of specified bit operations is a part of a compression process for compressing a bit stream.

Assignees

• Gopal Vinodh
• Guilford James D
• Wolrich Gilbert M
• Ozturk Erdinc
• Feghali Wajdi K
• Yap Kirk S
• Gulley Sean M
• Dixon Martin G
• Chappell Robert S
• Intel Corp

Inventors

• Gopal Vinodh
• Guilford James D
• Wolrich Gilbert M
• Ozturk Erdinc
• Feghali Wajdi K
• Yap Kirk S
• Gulley Sean M
• Dixon Martin G
• Chappell Robert S

Classifications

• G06F9/34

  Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30018

  Bit or string instructions · CPC title

• G06F9/30038

  using a mask · CPC title