Forming and operating memory devices that utilize correlated electron material (CEM)

Patent metadata

Field	Value
Publication number	US-10700280-B2
Application number	US-201916459518-A
Country	US
Kind code	B2
Filing date	Jul 1, 2019
Priority date	May 31, 2017
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

Subject matter disclosed herein may relate to fabrication of correlated electron materials (CEMs) devices used, for example, to read from a resistive memory element or to write to a resistive memory element. In embodiments, by limiting current flow through a CEM device, the CEM device may operate in the absence of Mott and/or Mott-like transitions in a way that brings about symmetrical diode-like operation of the CEM device.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of individually selectable memory devices, wherein at least a subset of the plurality of individually selectable memory devices individually comprise:
a memory element, and
a correlated electron material (CEM) device coupled in series with the memory element, wherein the CEM device to operate in a region of an impedance profile that is absent a Mott or Mott-like transition at least during write operations for the memory element.

2. The apparatus of claim 1 , wherein a resistance of the memory element operates the CEM device in the region of the impedance profile that is absent the Mott or Mott-like transition at least during the write operations for the memory element.

3. The apparatus of claim 1 , wherein the plurality of individually selectable memory devices are arranged in a cross-point array.

4. The apparatus of claim 1 , wherein one or more particular memory devices of the plurality of individually selectable memory devices are coupled between one or more particular electrodes of a first metal layer and one or more particular electrodes of a second metal layer.

5. The apparatus of claim 4 , wherein the one or more particular electrodes of the first metal layer to be electrically coupled to individual memory elements of the one or more particular memory devices of the plurality of individually selectable memory devices, and wherein the one or more particular electrodes of the second metal layer to be electrically coupled to individual OEM devices of the one or more particular memory devices of the plurality of individually selectable memory devices.

6. The apparatus of claim 5 , wherein the individual OEM devices of the one or more particular memory devices of the plurality of individually selectable memory devices to electrically couple the individual memory elements of the one or more particular memory devices of the plurality of individually selectable memory devices between the one or more particular electrodes of the first metal layer and the one or more particular electrodes of the second metal layer during write operations directed to the one or more particular memory devices.

7. The apparatus of claim 5 , wherein the one or more particular electrodes of the first metal layer comprise one or more wordlines and wherein the one or more particular electrodes of the second metal layer comprise one or more bitlines.

8. The apparatus of claim 1 , wherein the memory element to comprise a spin-transfer torque magnetic memory element or a resistive memory element, or a combination thereof.

9. The apparatus of claim 8 , wherein the resistive memory element to comprise a phase change memory element, a conductive bridging memory element or a nanotube memory element, or a combination thereof.

10. A method, comprising:
limiting a current flow through one or more individually selectable memory devices, the individually selectable memory devices individually comprising a memory element and a correlated electron material (OEM) device, to bring about write operations of the memory element absent a Mott or Mott-like transition in the OEM device.

11. The method of claim 10 , wherein the limiting the current flow through the one or more individually selectable memory devices comprises limiting the current flow at least in part via a resistance of the memory element.

12. The method of claim 10 , wherein the one or more individually selectable memory devices are coupled between one or more particular electrodes of a first metal layer and one or more particular electrodes of a second metal layer.

13. The method of claim 12 , wherein the limiting the current flow through the one or more individually selectable memory devices comprises limiting a current flow between the one or more particular electrodes of the first metal layer and the one or more particular electrodes of the second metal layer at least in part via a current-limiting circuit.

14. The method of claim 12 , further comprising applying a particular voltage across the one or more particular electrodes of the first metal layer and one or more particular electrodes of the second metal layer as part of the write operations for the memory element.

15. The method of claim 14 , wherein the one or more particular electrodes of the first metal layer to comprise one or more wordlines and wherein the one or more particular electrodes of the second metal layer comprise one or more bitlines.

16. The method of claim 10 , wherein the memory element to comprise a spin-transfer torque magnetic memory element or a resistive memory element, or a combination thereof.

17. The method of claim 16 , wherein the resistive memory element comprises a phase change memory element, a conductive bridging memory element or a nanotube memory element, or a combination thereof.

18. The method of claim 10 , wherein the one or more individually selectable memory devices are arranged in a cross-point array.

19. An array of individually selectable memory devices individually comprising:
a memory element; and
a correlated electron material (CEM) device coupled in series with the memory element, wherein a resistance of the memory element to limit current to operate the CEM device absent a Mott or Mott-like transition during write operations for the memory element.

20. The array of individually selectable memory devices of claim 19 , wherein the memory element to comprise a resistive memory element or a magnetic memory element, or a combination thereof, and wherein the CEM device to operate as a diode-type device.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Rosendale Glen Arnold
• Shifren Lucian

Classifications

• G11C2213/73

  Array where access device function, e.g. diode function, being merged with memorizing function of memory element · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C2213/15

  Current-voltage curve · CPC title

• G11C2013/0078

  Write using current through the cell · CPC title