Methods, systems, and computer program products for generating semiconductor circuit layouts

Patent metadata

Field	Value
Publication number	US-10699052-B2
Application number	US-201916528714-A
Country	US
Kind code	B2
Filing date	Aug 1, 2019
Priority date	Dec 18, 2014
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

First claim

What is claimed:

1. A system of generating electronic circuit layout data, the system comprising:
a processor circuit; and
an electronic storage medium configured to store a first standard cell layout, the first standard cell layout having a first scaling enhanced circuit layout and a marker layer, the first scaling enhanced circuit layout including a first-design-rule-violation-requiring region identified using the marker layer,
wherein the processor circuit is configured to:
receive data representing the first standard cell layout including the first scaling enhanced circuit layout,
generate a second scaling enhanced circuit layout including a second design-rule-violation-requiring region identified using the marker layer of the first scaling enhanced circuit layout,
swap the first scaling enhanced circuit layout for the second scaling enhanced circuit layout to provide data representing a second standard cell layout, and
verify the second scaling enhanced circuit layout using position defined by the marker layer.

2. The system of claim 1 ,
wherein the second scaling enhanced circuit layout is provided in a graphic database system (GDS) file, a GDS instance file or a hard macro file.

3. The system of claim 1 ,
wherein the first scaling enhanced circuit layout is formatted as a GDS instance file and the second scaling enhanced circuit layout is formatted as the GDS instance file.

4. The system of claim 1 ,
wherein the first scaling enhanced circuit layout is in a format of the GDS file and the second scaling enhanced circuit layout is in the format of the GDS file.

5. The system of claim 1 ,
wherein the second standard cell layout has a first region and a second region positioned adjacent to the first region, the second scaling enhanced circuit layout is arranged in the first region, and a circuit layout is arranged in the second region, and
wherein the processor circuit is configured to check a design rule of the circuit layout without checking a design rule of the second design-rule-violation-requiring region.

6. The system of claim 1 ,
wherein the first scaling enhanced circuit layout is part of the first standard cell layout to implement a function of a circuit.

7. The system of claim 1 ,
wherein the processor circuit is configured to receive a first logic block layout including the first standard cell layout and configured to provide a second logic block layout by swapping the first scaling enhanced circuit layout of the first logic block layout for the second scaling enhanced circuit layout.

8. The system of claim 1 ,
wherein the processor circuit is configured to:
generate the second scaling enhanced circuit layout;
add the marker layer of the first scaling enhanced circuit layout to the second scaling enhanced circuit layout, wherein the second scaling enhanced circuit layout includes a second design-rule-violation-requiring region identified using the marker layer;
generate a second standard cell layout by replacing the first scaling enhanced circuit layout of the first standard cell layout with the second scaling enhanced circuit layout having the marker layer; and
check a design rule on the second standard cell layout,
wherein the second design-rule-violation-requiring region is excluded in the checking of the design rule.

9. A computer program product, comprising:
a tangible computer readable storage medium comprising a computer readable program code embodied in the medium that when executed by a processor circuit causes the processor circuit to perform operations comprising:
allowing an electronic design automation tool to access data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium;
allowing the electronic design automation tool to generate a second scaling enhanced circuit layout, wherein the first scaling enhanced circuit layout and the second scaling enhanced circuit layout are identified using the same marker layer;
allowing the electronic design automation tool to replace the first scaling enhanced circuit layout with the second scaling enhanced circuit layout to provide data representing a second standard cell layout in the electronic storage medium; and
allowing the electronic design automation tool to verify the second scaling enhanced circuit layout using position defined by the marker layer.

10. The computer program product of claim 9 further comprising:
computer readable program code embodied in the medium that when executed by the processor circuit causes the processor circuit to perform operations comprising:
verifying that the data representing the second standard cell layout complies with a design rule,
wherein the second scaling enhanced circuit layout is excluded in the verifying.

11. The computer program product of claim 9 ,
wherein the first standard cell layout includes a third standard cell layout having a first region referring to the first scaling enhanced circuit layout, a fourth standard cell layout having a second region referring to the first scaling enhanced circuit layout, and
wherein allowing the electronic design automation tool to replace the first scaling enhanced circuit layout with the second scaling enhanced circuit layout comprises allowing the electronic design automation tool to replace the first scaling enhanced circuit layout referred to by the first and second regions with the second scaling enhanced circuit layout.

12. The computer program product of claim 9 ,
wherein the first standard cell layout includes a third standard cell layout having a first region in which the first scaling enhanced circuit layout is arranged, a fourth standard cell layout having a second region in which the first scaling enhanced circuit layout is arranged, and
wherein allowing the electronic design automation tool to replace the first scaling enhanced circuit layout with the second scaling enhanced circuit layout comprises:
allowing the electronic design automation tool to replace the first scaling enhanced circuit layout arranged in the third standard cell layout with the second scaling enhanced circuit layout, and
allowing the electronic design automation tool to replace the first scaling enhanced circuit layout arranged in the fourth standard cell layout with the second scaling enhanced circuit layout.

13. The computer program product of claim 9 ,
wherein the allowing of the electronic design automation tool to replace includes:
removing the first scaling enhanced circuit layout to form a blank region; and
replacing the blank region with the second scaling enhanced circuit layout.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Chul-Hong
• Kim Su-Hyeon
• Deepak Sharma

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10P95/00 Primary

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• Y10S148/085

  Isolated-integrated · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title