Translation support for a virtual cache

Patent metadata

Field	Value
Publication number	US-10698836-B2
Application number	US-201715625289-A
Country	US
Kind code	B2
Filing date	Jun 16, 2017
Priority date	Jun 16, 2017
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

First claim

What is claimed is:

1. A virtual cache directory, in a processor having virtual memory support and multiple threads, the virtual cache directory having a plurality of directory entries, each entry associated with a cache line, comprising:
a tag associated with each of the plurality of directory entries, the tag comprising:
a logical address;
an address space identifier;
a real address bit indicator;
a virtual address to real address indicator indicating that the logical address is the same as the real address;
and
a per thread validity bit for each thread that accesses the cache line.

2. The virtual cache directory of claim 1 wherein the cache line is configured to be shared by at least two different threads on a processor.

3. The virtual cache of claim 1 further comprising:
a line valid bit, the line valid bit indicating that at least one translation in the cache line is currently valid.

4. The virtual cache of claim 1 wherein when the virtual address to real address indicator is set, dynamic address translation is not performed.

Assignees

• IBM

Inventors

• Helms Markus
• Jacobi Christian
• Mayer Ulrich
• Recktenwald Martin
• Reichart Johannes C
• Saporito Anthony
• Tsai Aaron

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F2212/656

  Address space sharing · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title