Adaptive dynamic element matching of circuit components

Patent metadata

Field	Value
Publication number	US-10200054-B1
Application number	US-201815869757-A
Country	US
Kind code	B1
Filing date	Jan 12, 2018
Priority date	Jan 12, 2018
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

In a general aspect, an apparatus can include a signal analyzer configured to analyze a signal associated with a processing pipeline, and a dynamic element matching (DEM) selection module configured to select a DEM algorithm from a plurality of DEM algorithms based on the analysis performed by the signal analyzer. The apparatus can include a set of circuit elements where each circuit element from the set of circuit elements has the same logical configuration, and a circuit element selection module configured to select a subset of the set of circuit elements based on the selected DEM algorithm.

First claim

What is claimed is:

1. An apparatus, comprising:
a signal analyzer configured to analyze a signal associated with a processing pipeline;
a dynamic element matching (DEM) selection module configured to select a DEM algorithm from a plurality of DEM algorithms based on the analysis performed by the signal analyzer;
a set of circuit elements included in the processing pipeline, each circuit element from the set of circuit elements having an identical configuration; and
a circuit element selection module configured to select a subset of the set of circuit elements based on the selected DEM algorithm.

2. The apparatus of claim 1 , wherein the DEM algorithm is a first DEM algorithm, the signal analyzer analyzes the signal at a first time,
the signal analyzer is further configured to analyze the signal at a second time,
the DEM selection module is further configured to select a second DEM algorithm based on the analysis of the signal at the second time.

3. The apparatus of claim 2 , wherein the subset is a first subset, the circuit element selection module configured to select a second subset of the set of circuit elements based on the second DEM algorithm.

4. The apparatus of claim 1 , wherein the signal analyzer is configured to analyze at least one of a signal level or a signal frequency of the signal.

5. The apparatus of claim 1 , wherein the DEM selection module is configured to select the DEM algorithm based on the analysis of the signal and a condition stored in a memory.

6. The apparatus of claim 1 , further comprising:
a digital signal processor, at least one of the signal analyzer or the DEM selection module being included in the digital signal processor.

7. The apparatus of claim 1 , further comprising:
a digital-to-analog converter (DAC) processing pipeline, the set of circuit elements being included in the DAC processing pipeline.

8. The apparatus of claim 1 , wherein the signal is an input analog signal and the signal analyzer is configured to analyze the input analog signal,
the apparatus further comprising:
a digital-to-analog converter (DAC) configured to produce an output digital signal using the selected subset of circuit elements.

9. The apparatus of claim 1 , wherein at least one of the circuit elements includes a current source.

10. An apparatus, comprising:
a set of circuit elements, each circuit element from the set of circuit elements having the same configuration for processing signals;
a dynamic element matching (DEM) processor configured to use the set of circuit elements based on a first DEM algorithm;
a signal analyzer configured to analyze a signal; and
a dynamic element matching (DEM) selection module configured to select a second DEM algorithm from a plurality of DEM algorithms based on the analysis performed by the signal analyzer and a statistical condition, the second DEM algorithm being different from the first DEM algorithm.

11. The apparatus of claim 10 , further comprising:
a circuit element selection module configured to select a subset of the set of circuit elements based on the second DEM algorithm.

12. A method, comprising:
analyzing, during a first time period, a signal associated with a processing pipeline at a signal analyzer;
selecting a first DEM algorithm from a plurality of DEM algorithms based on the analysis during the first time period and a statistical condition;
selecting a subset of a set of circuit elements based on the selected first DEM algorithm, the selecting includes modifying a subset of a set of circuit elements in accordance with a pattern based on the selected DEM algorithm;
analyzing, during a second time period, the signal associated with the processing pipeline at the signal analyzer, the analyzing includes analyzing at least one of a signal level or a signal frequency of the signal; and
selecting a second DEM algorithm from the plurality of DEM algorithms based on the analysis during the second time period and the statistical condition.

13. The method of claim 12 , wherein the signal is a feedforward signal associated with an input side of the processing pipeline.

14. The method of claim 12 , wherein the signal is a feedback signal associated with an output side of the processing pipeline.

15. A method, comprising:
analyzing, during a first time period, a signal associated with a processing pipeline at a signal analyzer;
selecting a first DEM algorithm from a plurality of DEM algorithms based on the analysis during the first time period and a statistical condition;
selecting a subset of a set of circuit elements based on the selected first DEM algorithm, the first DEM algorithm being an equation that moves an error associated with the set of circuit elements to an out-of-band portion of a frequency spectrum of the signal;
analyzing, during a second time period, the signal associated with the processing pipeline at the signal analyzer; and
selecting a second DEM algorithm from the plurality of DEM algorithms based on the analysis during the second time period and the statistical condition.

16. The method of claim 12 , wherein the signal is an input analog signal,
the method further comprising:
producing an output digital signal using the selected subset of circuit elements.

17. The method of claim 12 , the selecting the first DEM algorithm includes selecting during the first time period.

18. The apparatus of claim 1 , wherein the signal is a feedforward signal associated with an input side of the processing pipeline or feedback signal associated with an output side of the processing pipeline.

19. The method of claim 15 , wherein the signal is a feedforward signal associated with an input side of the processing pipeline or feedback signal associated with an output side of the processing pipeline.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Jasa Hrvoje
• Daigle Tyler
• Jordan Andrew
• Maher Gregory

Classifications

• H03M3/502

  Details of the final digital/analogue conversion following the digital delta-sigma modulation · CPC title

• H03M1/0673

  using random selection of the elements (with data-controlled random generator H03M1/0665) · CPC title

• H03M1/74

  Simultaneous conversion · CPC title

• H03M1/664

  Non-linear conversion not otherwise provided for in subgroups of H03M1/66 · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title