Adaptive toggle number compensation for reducing data dependent supply noise in digital-to-analog converters

Patent metadata

Field	Value
Publication number	US-10693483-B1
Application number	US-201916542602-A
Country	US
Kind code	B1
Filing date	Aug 16, 2019
Priority date	Aug 16, 2019
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

Adaptive toggle number compensation techniques for reducing data dependent supply noise in DACs are disclosed. Various embodiments are based on setting a certain target toggle number for a plurality of DAC units used to convert at least a portion of a digital data sample and then applying various adaptive techniques to try to achieve the target toggle number in converting the data sample from digital to analog domain. Adaptive toggle number compensation techniques described herein try to reduce data dependent supply noise by deliberately limiting, to a certain target number, the number of DAC units that undergo a switch from the digital input of 1 to 0 or from 0 to 1 in converting a digital data sample. Compared to the conventional dummy signal generation approach, such adaptive toggle number compensation techniques may provide significant savings in terms of power consumption of a DAC.

First claim

The invention claimed is:

1. A digital-to-analog converter (DAC) system, comprising:
a first plurality of DAC units;
a second plurality of DAC units, where each DAC unit of the first plurality of DAC units and the second plurality of DAC units is configured to operate in one of two states to convert digital samples to analog values; and
a controller configured to:
select one or more DAC units of the first plurality of DAC units and the second plurality of DAC units to operate in a first state of the two states during conversion of a second digital sample to a second analog value,
operate the one or more DAC units in the first state during conversion of the second digital sample, and
operate unselected DAC units of the first plurality of DAC units and the second plurality of DAC units in a second state of the two states during conversion of the second digital sample;

wherein the one or more DAC units are selected so that a number of DAC units of the first plurality of DAC units and the second plurality of DAC units that switch from operating in the first state during conversion of a first digital sample to a first analog value to operating in the second state during conversion of the second digital sample and that switch from operating in the second state during conversion of the first digital sample to operating in the first state during conversion of the second digital sample is equal to a target toggle number, where the first digital sample and the second digital sample are consecutive digital samples of an input signal to the DAC system.

2. The DAC system according to claim 1 , wherein the first plurality of DAC units is thermometer-coded and the second plurality of DAC units is binary-coded.

3. The DAC system according to claim 1 , wherein the first digital sample is an intermediate significant bit (ISB) portion of a first digital input value and the second digital sample is an ISB portion of a second digital input value.

4. The DAC system according to claim 3 , wherein the DAC further includes a third plurality of DAC units configured to convert most significant bit (MSB) portions of the first digital input value and the second digital input value.

5. The DAC system according to claim 4 , wherein:
each of the first plurality of DAC units and the third plurality of DAC units is thermometer-coded,
at least some of the second plurality of DAC units are binary-coded, and
a coding weight of the MSB DAC unit of the second plurality of DAC units is equal to a coding weight of one DAC unit of the third plurality of DAC units.

6. The DAC system according to claim 4 , wherein the controller is further configured to:
select one or more DAC units of the third plurality of DAC units to operate in the first state during conversion of the MSB portion of the second digital input value,
operate the one or more DAC units of the third plurality of DAC units in the first state during conversion of the MSB portion of the second digital input value, and
operate unselected DAC units of the third plurality of DAC units in the second state during conversion of the MSB portion of the second digital input value,
wherein the one or more DAC units of the third plurality of DAC units are selected so that a number of DAC units of the third plurality of DAC units that switch from operating in the first state during conversion of the MSB portion of the first digital input value to operating in the second state during conversion of the MSB portion of the second digital input value and that switch from operating in the second state during conversion of the MSB portion of the first digital input value to operating in the first state during conversion of the MSB portion of the second digital input value is equal to a second target toggle number.

7. The DAC system according to claim 6 , wherein the controller is configured to set the target toggle number and the second target toggle number so that a sum of the target toggle number and the second target toggle number is equal to a target total toggle number.

8. The DAC system according to claim 1 , further comprising an adder configured to:
add outputs of the first plurality of DAC units and outputs of the second plurality of DAC units generated by operating the one or more selected DAC units and the unselected DAC unit during conversion of the first digital sample to generate an analog value indicative of the first analog value, and
add outputs of the first plurality of DAC units and outputs of the second plurality of DAC units generated by operating the one or more selected DAC units and the unselected DAC unit during conversion of the second digital sample to generate an analog value indicative of the second analog value.

9. The DAC system according to claim 1 , wherein the controller is configured to select the one or more DAC units so that the number of DAC units of the first plurality of DAC units and the second plurality of DAC units that switch from operating in the first state during conversion of the first digital sample to operating in the second state during conversion of the second digital sample and that switch from operating in the second state during conversion of the first digital sample to operating in the first state during conversion of the second digital sample is equal to the target toggle number for each pair of consecutive digital samples of the input signal.

10. The DAC system according to claim 1 , wherein the controller is configured to select the one or more DAC units by providing a first control signal to the one or more DAC units and by providing a second control signal, different from the first control signal, to the unselected DAC units.

11. The DAC system according to claim 10 , wherein one control signal of the first control signal and the second control signal includes a first logic state and another control signal of the first control signal and the second control signal includes a second logic state.

12. A digital-to-analog converter (DAC) system, comprising:
a plurality of DAC units, where each DAC unit of the plurality of DAC units is configured to operate in one of two states to convert digital samples to analog values; and
a controller configured to:
select one or more DAC units of the plurality of DAC units to operate in a first state of the two states during conversion of a second digital sample to a second analog value,
operate the selected one or more DAC units in the first state during conversion of the second digital sample, and
operate unselected DAC units of the plurality of DAC units in a second state of the two states during conversion of the second digital sample;

wherein the one or more DAC units are selected so that a number of DAC units of the plurality of DAC units that switch from operating in the first state during conversion of a first multi-bit digital sample to a first analog value to operating in the second state during conversion of the second digital sample and that switch from operating in the second state during conversion of the first digital sample to operating in the first state during conversion of the second digital sample is equal to a target toggle number, where the first digital sample and the second digital sample are consecutive digital samples of an input signal to the DAC system.

13. The DAC system according to claim 12 , wherein the plurality of DAC units is thermometer-coded.

14. The DAC system according to claim 12 , wherein the first digital sample is a most significant bit (MSB) portion of a first digital input value and the second digital sample is an MSB portion of a second digital input value.

15.

Assignees

• Analog Devices International Unlimited Co

Inventors

• Luo Hao
• Kuo Shawn S
• Zhao Jialin
• Rose Steven
• Li Dong
• Zhang Lin
• Wang Tommi

Classifications

• H03M7/3015

  Structural details of digital delta-sigma modulators · CPC title

• H03M1/687

  Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type · CPC title

• H03M1/0863 Primary

  of switching transients, e.g. glitches · CPC title

• H03M1/0639

  using dither, e.g. using triangular or sawtooth waveforms (for increasing resolution H03M1/201) · CPC title

• H03M1/0836 Primary

  of phase error, e.g. jitter · CPC title