Digital-to-analog converter (DAC) with partial constant switching

Patent metadata

Field	Value
Publication number	US-9800254-B2
Application number	US-201615130602-A
Country	US
Kind code	B2
Filing date	Apr 15, 2016
Priority date	Apr 16, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Systems and methods are provided for digital-to-analog converter (DAC) with partial constant switching. A digital-to-analog converter (DAC) comprising a plurality of conversion elements may be configured to apply constant switching in only some of the conversion elements. Only conversion elements applying constant switching may incorporate circuitry for providing such the constant switching. Alternatively, each conversion element may incorporate constant switching circuitry and functionality, and the constant switching may then be turned on or off for each conversion element adaptively, such as based on input conditions.

First claim

What is claimed:

1. A method for managing digital-to-analog conversions in a digital-to-analog converter (DAC), comprising:
determining switching characteristics for a plurality of conversion elements in the DAC, wherein each conversion element handles a particular bit in a digital input to the DAC; and
configuring constant switching in said DAC based on determined switching characteristics, wherein said configuring comprises applying constant switching in only a subset of the plurality of conversion elements.

2. The method of claim 1 , wherein said determining of switching characteristics comprises determining for each conversion element whether that conversion element switches or not for particular input conditions.

3. The method of claim 2 , wherein said subset of the plurality of conversion elements comprises one or more conversion elements that are determined to switch for said particular input conditions.

4. The method of claim 1 , comprising determining each conversion element in said subset of the plurality of conversion elements during design of said DAC.

5. The method of claim 1 , comprising incorporating constant switching function only in each conversion element in said subset of the plurality of conversion elements.

6. The method of claim 1 , wherein:
each conversion element of the plurality of conversion elements incorporates a constant switching function; and
said configuring of constant switching in said DAC comprises dynamically enabling or disabling the constant switching function in each conversion element during operation of the DAC.

7. The method of claim 6 , comprising:
determining switching characteristics for each conversion element in the plurality of conversion elements for particular input conditions; and
determining whether to enable or disable the constant switching function in each conversion element based on switching characteristics for that conversion element that are determined based on said particular input conditions.

8. The method of claim 7 , wherein said particular input conditions comprise signal backoff.

9. A system comprising:
a digital-to-analog converter (DAC) that is operable to apply digital-to-analog conversions, the DAC comprising a plurality of conversion elements with each conversion element configured to handle a particular bit in a digital input to the DAC, wherein:
the DAC is operable to support partial constant switching;
the partial constant switching comprises applying constant switching in only a subset of the plurality of conversion elements; and
the partial constant switching is configured based on switching characteristics for the plurality of conversion elements.

10. The system of claim 9 , wherein switching characteristics comprise a determination for each conversion element whether that conversion element switches or not for particular input conditions.

11. The system of claim 10 , wherein said subset of the plurality of conversion elements comprises one or more conversion elements that are determined to switch for said particular input conditions.

12. The system of claim 9 , wherein each conversion element in said subset of the plurality of conversion elements is determined during design of said DAC.

13. The system of claim 9 , wherein only each conversion element in said subset of the plurality of conversion elements comprises one or more circuits for applying a constant switching function.

14. The system of claim 9 , wherein:
each conversion element of the plurality of conversion elements comprises one or more circuits for applying a constant switching function; and
said DAC comprises one or more control circuits for dynamically enabling or disabling the constant switching function in each conversion element during operation of the DAC.

15. The system of claim 14 , wherein said one or more control circuits are operable to:
determine switching characteristics for each conversion element in the plurality of conversion elements for particular input conditions; and
determine whether to enable or disable the constant switching function in each conversion element based on switching characteristics for that conversion element that are determined based on said particular input conditions.

16. The system of claim 15 , wherein said particular input conditions comprise signal backoff.

17. The system of claim 9 , wherein the DAC comprises segmentation-based implementation, comprising a plurality of segments, with each segment comprising one or more conversion elements of the plurality of conversion elements.

18. The system of claim 17 , wherein the plurality of segments comprises:
a most significant bits (MSBs) segment; and
one or more least significant bits (LSBs) segments.

19. The system of claim 18 , wherein the one or more LSBs segments comprise:
a lower least significant bits (LLSBs) segment;
a middle least significant bits (MLSBs) segment; and
an upper least significant bits (ULSBs) segment.

20. The system of claim 18 , wherein only one or more conversion elements in the MSBs segment and all conversion elements in the one or more LSBs segments are operable to apply constant switching.

Assignees

• Maxlinear Inc

Inventors

• Chandra Gaurav
• Zeng Tao
• Swaroop Shantha Murthy Prem
• Zhu Jianyu

Classifications

• H03M1/0624 Primary

  by synchronisation · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title